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Testa
Account closed
Registered: Oct 2004
Posts: 197 |
fetch the 0-sprite. with open borders...
hi,
ik have a little problem.. i want to open the sideborders with the 4 lowest sprites... i have two questions about it..
when i do the D016 write i use a dec d016 or a lsr or ror as opcode... why does a sty, sta, stx not work....
has it something to do with cpu takeover cycles at that point...
second question... what to do on a badline....
there are not enough free cycles. with 4 sprites for a inc, ror or lsr d016 instead of a sta, sty or stx...
i realize it is common knowledge.. but sorry i dont. know it...
bye...
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Oswald
Registered: Apr 2002
Posts: 5034 |
@mr I know better how c64 and atari DMA works,
>>no, I mean on the c64 you have this 3 cycle zone, while atari does not have this.
>it should be there too, but unlike its done in the c64, they used a much simplier approach to implement it, and halt the cpu regardless if it could still perfom the read cycles or not.
- the cpu stops on the 1st read cycle -> you should have written write cycle :P
- if you stop the cpu regardless of the read(write) cycle you dont need 3 cycle safety zone.
- its obvious you have no idea how it works on the atari, just some vague ones :) |
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chatGPZ
Registered: Dec 2001
Posts: 11165 |
no, thats not the problem. there are even two clocks (dotclock and phi2). the "problem" is that the timing at the port isn't all that great (and worse, shifts a bit over time), and you have to gate several signals with either ba or rw "manually" so you can read/write/assert other signals like dma (or even just adress and/or data) at the right time, and that not only for the reason the vic has to use aec/rdy. it's a bit more complex than you think :) its somewhat like "remote controlling" the signals that control the cpu, but "through" the vic instead. (eg the vic controls the cpu by rdy and aec, on the expansion port you have ba and dma instead, which serve a similar purpose, but not exactly). (and at this point some hardware guy should take over, because i really cant explain it without some bus diagrams)
"- if you stop the cpu regardless of the read(write) cycle you dont need 3 cycle safety zone."
but you CANT stop the cpu during a write cycle, read what ninja wrote. and you need the safety zone to make sure the rw line is in the correct state when you take over. |
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Oswald
Registered: Apr 2002
Posts: 5034 |
on the expansion port, I thought you were talking about problems of the atari one, and asked about that :)
2nd part:
but you can. We're talking of Ataris now, and they had a modded 6502 with a HALT line, also IIRC before this they had a mechanism which simply stopped the clock signal. anyway googling doesnt helps me finding more info on this, but I bet a simpler mechanism than c64's means no 3 cycle puffer zone. |
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chatGPZ
Registered: Dec 2001
Posts: 11165 |
Quote:on the expansion port, I thought you were talking about problems of the atari one, and asked about that :)
no :) the atari one seems to miss signals like BA, and there is no phi2 and no dotclock, which makes gating signals (and doing various dirty tricks in particular) a lot harder, if not impossible. (that said, i dont know wether such tricks are needed or possible on ataris. on the c64 you can do fun stuff like putting data ment for the vic on the bus externally this way, for example)
Quote:but you can. We're talking of Ataris now, and they had a modded 6502 with a HALT line, also IIRC before this they had a mechanism which simply stopped the clock signal. anyway googling doesnt helps me finding more info on this, but I bet a simpler mechanism than c64's means no 3 cycle puffer zone.
didnt find detail info either, but "It is identical to the standard 6502 except that it has a HALT input for stopping the processor and tri-stating the system bus so that other chips in the system can do DMA." implies that the logic needed to stop a regular 6502 (by using aec and rdy) was simply moved into the cpu. indeed, this could possibly mean no _3_ cycle buffer zone is needed, maybe 1 is enough.
(btw, simply stopping the clock doesnt work, that again you cant do in a write cycle, because rw would stay low, with the consequences ninja explained. you could stop the clock, assert rdy, and then pray everything goes well though =P) |
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Oswald
Registered: Apr 2002
Posts: 5034 |
cool, glad we could sort it out afterall :) |
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chatGPZ
Registered: Dec 2001
Posts: 11165 |
the downside is: no i am curious about how they really did it. and there doesnt seem to be any 6502C datasheet online anywhere, and all the atari FAQs suck =P |
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Testa
Account closed
Registered: Oct 2004
Posts: 197 |
Quote: See this graph: In cycles marked with "X" (during takeover), writing is possible, reading not. RMW opcodes are special because their last *two* cycles are write-cycles. This way, you can still access the cycle yo need for opening the border. STA has just the final cycle as write cycle, that is not enough.
thanks ninja.. so on a good line there is no problem when you use RMW opcodes... but on a bad line it is not possible becoz BA will be low at cycle 56....
i have read the vic article about this and i understand it better now.....
well thanks anyway
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Monte Carlos
Registered: Jun 2004
Posts: 351 |
The discussion is very interesting, but perhaps a little too technical and therefore i doubt, that it is really helpful for someone asking about it.
There is one rule, which is probably more adequate:
- Use always the last sprites in row when opening the sideborder instead of the first ones and you will not experience most of these problems. So in this case sprites 4,5,6 and 7 would be appropriate.
Greetz Monte
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Mace
Registered: May 2002
Posts: 1799 |
Monte, that is the general rule.
Testa however wanted to find a way to use sprite 0, despite common knowledge that this is impossible.
Oh noes... did I say 'IMPOSSIBLE'...?
Now I triggered Crossbow! |
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Jetboy
Registered: Jul 2006
Posts: 242 |
Would it be possible to use sprite 0 with reu ? |
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