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Krill
Registered: Apr 2002
Posts: 2980 |
$D016 bit 5
There is this mysterious bit early on in the KERNAL reset routine:
FCEF: 8E 16 D0 STX $D016 ; VIC: Control Register 2 with X being anything in [0..5].
Now, some people [who?] claim that without this store to $d016, some [which?] cartridges won't start [citation needed].
However, $D016 apparently used to have a mysterious "reset bit" in supposedly early VIC-II revisions (those with only 5 not 9 luma steps, and then the early ones of those).
| Bit 5 | Reset-Bit: 1 = Stop VIC (no Video Out, no RAM |
| | refresh, no bus access) | Could this be the reason why some things on some machines (?) won't start without that store to $D016?
Do any machines still exist where setting $D016 to, say, $f8 would crash them (when running code from RAM)?
Or did this "reset bit" never exist? =) |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Although the programmer's reference guide does show d016 db5 as "RST" high. Hmm :)
The reset cartridge test at $fd02 does happen very early on after machine reset, the jsr does use the stack though. Hypothetically if the VIC defaults to being "in reset" and the memory refresh is off, this might mean the memory for the stack could fail... For the same/similar reason some machines fail with the VIC HSP using a "DMA delay" (DRAM refresh or whatever you want to call it) screen scroll.
Theoretically the delay between setting the stack memory, checking the cart, and reading the stack back with an rts could be small enough to not experience memory corruption.
This might explain why the $d016 set without "reset" is very early in the reset code, to make sure the VIC is refreshing memory...
All this would need to be tested if there are any VICs that do default to "reset on" and do not refresh the DRAM. |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Although the HSP/VSP DRAM issue does seem to be related to unexpected DRAM refresh signal timings, rather than lack of refresh timings. DRAM that isn't refreshed *at all* would tend to decay slower than badly refreshed DRAM due to signals flickering unexpectedly. |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
<offtopic>"VSP Bug" is not related to refresh - see LFTs article</offtopic> |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: <offtopic>"VSP Bug" is not related to refresh - see LFTs article</offtopic>
Incorrect, see "In short, one memory cell gets refreshed with the bit value of a different memory cell." |
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Oswald
Registered: Apr 2002
Posts: 5094 |
while we're at it, someone could enlighten me how is this ram refresh is done ? I mean like ram bus is 2mhz, where is the extra time VIC has access to the ram ? is this done by reading the contents? etc |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
Quote:Incorrect, see "In short, one memory cell gets refreshed with the bit value of a different memory cell."
You didn't understand the article. Its a ras/cas timing violation. Also see the first paragraph. |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: while we're at it, someone could enlighten me how is this ram refresh is done ? I mean like ram bus is 2mhz, where is the extra time VIC has access to the ram ? is this done by reading the contents? etc
https://c64os.com/post/flitiming1
Look for the text "The top two lines show /RAS and /CAS."
It seems to be a good explanation. |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: Quote:Incorrect, see "In short, one memory cell gets refreshed with the bit value of a different memory cell."
You didn't understand the article. Its a ras/cas timing violation. Also see the first paragraph.
Incorrect. I understand perfectly, that why I wrote the correct comments in the post above "unexpected DRAM refresh signal timings" and "badly refreshed DRAM due to signals flickering unexpectedly".
Note how what I wrote corresponds to the "which means that its output will flicker rapidly" from the article. |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
>_< |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: >_<
You just don't understand what I wrote and how it's basically identical to the article. That's OK. |
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