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Krill
Registered: Apr 2002
Posts: 2845 |
Shortest code for stable raster timer setup
While working on my ICC 2019 4K entry (now postponed to ICC 2020, but i hope it'll be worth the wait), i came up with this (14 bytes):initstabilise lda $d012
ldx #10 ; 2
- dex ; (10 * 5) + 4
bpl - ; 54
nop ; 2
eor $d012 - $ff,x; 5 = 63
bne initstabilise; 7 = 70
[...]; timer setupThe idea is to loop until the same current raster line is read at the very beginning (first cycle) and at the very end (last cycle) of a raster line, implying 0 cycles jitter.
With 63 cycles per line on PAL, the delay between the reads must be 63 cycles (and not 62), reading $d012 at cycle 0 and cycle 63 of a video frame's last line (311), which is one cycle longer due to the vertical retrace.
The downside is that effectively only one line per video frame is attempted, so the loop may take a few frames to terminate, and the worst case is somewhere just beyond 1 second.
The upside is that it always comes out at the same X raster position AND raster line (0), plus it leaves with accu = 0 and X = $ff, which can be economically re-used for further init code.
Now, is there an even shorter approach, or at least a same-size solution without the possibly-long wait drawback? |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
Thanks! That makes it a lot clearer. So the possibibilty of having 462 cycles due to the W-cycle can result in a periodic loop that excludes the "golden" R-cycle that would end the loop.
I think though that the borders could make some of the other loop lengths work.
The border is 112*63 cycles = 7056 cycles.
So perhaps a loop, when it is stuck in a wrong loop on the visible screen, will be "shifted out" of that loop in the border.
This will happen for a loop length of 17, since 7056 = 415*17 + 1.
Loop lengths 11, 13, and 15 still don't seem to work.
(Btw, with longer loop lengths there may be more W-cycles in the loop.) |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
Quoting CopyfaultSo next task is to get his <7 bytes *ducks+runs*
Here is one example of a six bytes loop. ZP-address $39 contains the basic line number. So that one is free to choose, if we choose 17 decimal, then all registers will contain $11 after the SYS with the code:
17 SYS 14774 : REM $39B6
*=$39B4 (14772 decimal)
39B4 loop: TAY
39B5 SHX $39A7,Y
39B8 BPL loop
The SYS 14774 jumps to LAX $39, which contains $11. Since $3A AND $11 equals $10, the SHX stores the BPL opcode at $39B8, except when the &{H+1} drops off due to DMA. Then it stores opcode $11, which is ORA (ZP),Y and the loop exits.
Surely there are other working examples, with perhaps more convenient addresses? |
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Quiss
Registered: Nov 2016
Posts: 37 |
Quoting Rastah Bar
I think though that the borders could make some of the other loop lengths work.
The border is 112*63 cycles = 7056 cycles.
So perhaps a loop, when it is stuck in a wrong loop on the visible screen, will be "shifted out" of that loop in the border.
This will happen for a loop length of 17, since 7056 = 415*17 + 1.
Oh, good point! Indeed, loop length of 17 gets "fixed" by the border. Depending on which cycle you land on initially, loop exit gets delayed by up to three frames, but it'll eventually align.
A similar thing happens with 27, which takes up to four frames to align.
Those seem to be the only "special" (multi-frame) cases below 30.
Quoting Rastah Bar
(Btw, with longer loop lengths there may be more W-cycles in the loop.)
Right. Any extra W cycles would make things more complicated. I guess they could both break loops and create loops. |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
The six byte example as shown does not work since it could get interrupted. An SEI should be executed first before jumping into the loop. |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Quoting Rastah BarThe six byte example as shown does not work since it could get interrupted. An SEI should be executed first before jumping into the loop.
Hmm, this is more or less the same for all examples we had before, or do I miss smth?? Ok, here a basic sys-line is part of the trick, but it could also jump to an init routine that does SEI or LDA #$7F:STA $DC0D:etc. first.
Another instability of the approach with having the operand bytes of the SHX actually doing something usefull (i.e. filling a register) is that y != 0 in all the examples we had until now. This can lead to the ORA ($f9),Y taking one cycle more, depending on the content of $f9/$fa.
So I vote for $14 instead of $11 as value for X. It'll change the BPL into a NOP zp,X which always takes 4 cycles. |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
It can be fixed by putting an SEI in a 7 byte loop. Adding your improvement as well:
20 SYS 14777 : REM $39B9
*=$39B6 (14774 decimal)
39B6 loop: SEI
39B7 TAY
39B8 SHX $39A7,Y
39BB BPL loop
But since the basic SYS 14777 instruction occupies one more byte in memory than a SYS to $08xx, I suppose we have to count this as an eight bytes method. |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Quoting QuissNeat! Right, no reason to make those two address bytes go to waste. :)
Another amusing thing to contemplate is how this code could be placed at, say, $08xx. Preferably without messing up the basic upstart.
[...] Not necessarily the shortest piece of code, but it satisfies your requirement to have the sync routine at $08xx:
0843 A2 9E LDX #$9E
0845 A0 08 LDY #$08
0847 E0 00 CPX #$00
0849 D0 F9 BNE $0844
Branching to $0844 leads to SHX $08A0,Y, so the operand byte of the CPX is altered continuously. As long as the "&(hi+1)" plays in, the compare operand will be =$08. When "&(hi+1)" disappears, the full $9E is written to the operand byte and the loop will end. This happens iff the critical SHX-cycle happens on a badline. |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
Excellent! |
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Jammer
Registered: Nov 2002
Posts: 1289 |
Stupid question from a layman - where this stabilizing piece of code is supposed to go exactly to do its job and not crash the whole thing? :) |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
$08A3 |
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