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Krill
Registered: Apr 2002
Posts: 2965 |
$D016 bit 5
There is this mysterious bit early on in the KERNAL reset routine:
FCEF: 8E 16 D0 STX $D016 ; VIC: Control Register 2 with X being anything in [0..5].
Now, some people [who?] claim that without this store to $d016, some [which?] cartridges won't start [citation needed].
However, $D016 apparently used to have a mysterious "reset bit" in supposedly early VIC-II revisions (those with only 5 not 9 luma steps, and then the early ones of those).
| Bit 5 | Reset-Bit: 1 = Stop VIC (no Video Out, no RAM |
| | refresh, no bus access) | Could this be the reason why some things on some machines (?) won't start without that store to $D016?
Do any machines still exist where setting $D016 to, say, $f8 would crash them (when running code from RAM)?
Or did this "reset bit" never exist? =) |
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Oswald
Registered: Apr 2002
Posts: 5084 |
while we're at it, someone could enlighten me how is this ram refresh is done ? I mean like ram bus is 2mhz, where is the extra time VIC has access to the ram ? is this done by reading the contents? etc |
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chatGPZ
Registered: Dec 2001
Posts: 11334 |
Quote:Incorrect, see "In short, one memory cell gets refreshed with the bit value of a different memory cell."
You didn't understand the article. Its a ras/cas timing violation. Also see the first paragraph. |
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Martin Piper
Registered: Nov 2007
Posts: 711 |
Quote: while we're at it, someone could enlighten me how is this ram refresh is done ? I mean like ram bus is 2mhz, where is the extra time VIC has access to the ram ? is this done by reading the contents? etc
https://c64os.com/post/flitiming1
Look for the text "The top two lines show /RAS and /CAS."
It seems to be a good explanation. |
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Martin Piper
Registered: Nov 2007
Posts: 711 |
Quote: Quote:Incorrect, see "In short, one memory cell gets refreshed with the bit value of a different memory cell."
You didn't understand the article. Its a ras/cas timing violation. Also see the first paragraph.
Incorrect. I understand perfectly, that why I wrote the correct comments in the post above "unexpected DRAM refresh signal timings" and "badly refreshed DRAM due to signals flickering unexpectedly".
Note how what I wrote corresponds to the "which means that its output will flicker rapidly" from the article. |
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chatGPZ
Registered: Dec 2001
Posts: 11334 |
>_< |
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Martin Piper
Registered: Nov 2007
Posts: 711 |
Quote: >_<
You just don't understand what I wrote and how it's basically identical to the article. That's OK. |
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chatGPZ
Registered: Dec 2001
Posts: 11334 |
Yes, that's it! |
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Martin Piper
Registered: Nov 2007
Posts: 711 |
In other words, from what I wrote earlier, "unexpected DRAM refresh signal timings" (RAS and CAS and the address lines) "flickering unexpectedly" causes "badly refreshed DRAM" aligns with the article "one memory cell gets refreshed with the bit value of a different memory cell". It is precisely to do with refresh of DRAM, or rather bad or faulty refresh in this case. |
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chatGPZ
Registered: Dec 2001
Posts: 11334 |
The DRAM refresh happens in the refresh cycles. There is no problem there.
You can write "incorrect" once more. |
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tlr
Registered: Sep 2003
Posts: 1785 |
Quoting KrillHowever, $D016 apparently used to have a mysterious "reset bit" in supposedly early VIC-II revisions (those with only 5 not 9 luma steps, and then the early ones of those).
The reset bit does not do anything on the 6569R1. I'm guessing early 6567's, maybe only prototypes even? |
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