| |
TWW
Registered: Jul 2009
Posts: 545 |
$dc0d madness
how come a lot of people set up their raster IRQ's like:
lda #$01
sta $d01a
lda #$7f (?)
sta $dc0d
and not just simply:
ldx #$00 // I believe 0 = mask and 1 = don't mask but it isn't specified in the prog.ref.manual...
stx $dc0d // Mask out all CIA#1 IRQ's
inx
stx $d01a // Mask out all VICII IRQ's minus raster compare
Where does this "#$7f" come from?
or have i missed some kind of importaint point here? |
|
... 11 posts hidden. Click here to view all posts....
|
| |
Stone
Registered: Oct 2006
Posts: 172 |
No points for you! Come back, one year! |
| |
TWW
Registered: Jul 2009
Posts: 545 |
I also came to think about the IRQ being pulled low by an event. How long does it take before another IRQ is triggered (coz as I understand it it is the low state not the state change which triggers the IRQ(unlike NMI which relies on state change))?
Stein wtf? |
| |
Stone
Registered: Oct 2006
Posts: 172 |
Bit 7 being set on write wont disable the IRQs, it will enable them (but they're already enabled, so it's a no-op). In the case where bit 7 is 0, no CIA1 IRQs are enabled, so this is also a no-op. |
| |
TWW
Registered: Jul 2009
Posts: 545 |
Quote: Bit 7 being set on write wont disable the IRQs, it will enable them (but they're already enabled, so it's a no-op). In the case where bit 7 is 0, no CIA1 IRQs are enabled, so this is also a no-op.
Stolen from AAY64:
$DC0D/56333/CIA1+13: Interrupt (IRQ) Control Register
+-------+------------------------------------------------------+
| Bit 7 | On Read: 1 = Interrupt occured |
| | On Write: 1 = Set Int.-Flags, 0 = Clear Int-.Flags |
| Bit 4 | FLAG1 IRQ (Cassette Read / Serial Bus SRQ Input) |
| Bit 3 | Serial Port Interrupt ($DC0C full/empty) |
| Bit 2 | Time-of-Day Clock Alarm Interrupt |
| Bit 1 | Timer B Interrupt (Tape, Serial Port) |
| Bit 0 | Timer A Interrupt (Kernal-IRQ, Tape) |
+-------+------------------------------------------------------+
On Write: 1 = Set Int.-Flags!
stolen from c64prg:
DC0D 56333 CIA Interrupt Control Register
(Read IRQs/Write Mask)
7 IRQ Flag (1 = IRQ Occurred) / Set-
Clear Flag
4 FLAG1 IRQ (Cassette Read / Serial Bus
SRQ Input)
3 Serial Port Interrupt
2 Time-of-Day Clock Alarm Interrupt
1 Timer B Interrupt
0 Timer A Interrupt
in the bible it says WRITE MASK where Set (1) will clear the flag in contradiction to the AAY64 where it sais 1 = set the flag.
So I got it half right due to shady intel...
This means Oswalds half point is withdrawn.
ps. the masking is the oposite then on the VIC where it is called the mask register and a set bit indicates mask... |
| |
Stone
Registered: Oct 2006
Posts: 172 |
My reply was a bit clumsily put. What I meant was, when bit 7 is 0, writing back any remaining 1-bits will do nothing, since their corresponding IRQ is already disabled. And yes, you got it half right. |
| |
Frantic
Registered: Mar 2003
Posts: 1648 |
[edit] |
| |
TWW
Registered: Jul 2009
Posts: 545 |
Quote: My reply was a bit clumsily put. What I meant was, when bit 7 is 0, writing back any remaining 1-bits will do nothing, since their corresponding IRQ is already disabled. And yes, you got it half right.
The only way bit #7 is clear when you read $dc0d is if there are no IRQ's (The whole point of reading $dc0d is to determine which IRQ got activated besides ack any pending irqs(as I understand it)). so in your example above above would simply be the same as:
lda $dc0d (which with no triggered irqs equals #0(aka lda #0))
sta $dc0d
which would totally do nothing but mess up A and waste some cycles (hence a fail).
if some IRQs got triggered bit #7 would be set and whatever bit 6-0 would be set.
Writing this back would set any corresponding flags high (and in contradiction to $d01a which masks them it will here allow them to occur). Given the fact that they already occured (meaning they where already allowed) it makes no point to allow them more then they already are. also a fail. :)
conclusion: a lda/sta $dc0d does absolutely nothing but ack CIA IRQs, waste cycles and destroy A.
Stick a fork in me I'm done.
However I am still curious about the time it takes for another IRQ to occur if the IRQ event remains unack'ed? |
| |
Stone
Registered: Oct 2006
Posts: 172 |
Consider yourself stuck |
| |
Stone
Registered: Oct 2006
Posts: 172 |
EDIT:Quoting Stein What I meant was, when bit 7 is 0, writing back any remaining 1-bits will do nothing But ofcourse, there are no remaining 1-bits. Man, it's been too long... |
| |
TNT
Account closed
Registered: Oct 2004
Posts: 189 |
Quoting TWWWhat I find interesting is that SEI itself only inhibit activation of IRQs but don't stop them from setting bits high in $d019/$dc0d even during a sei-cli.
SEI affects CPU only, your interrupt sources are two CIAs and VIC-II. 6510 doesn't generate any interrupts (except BRK which doesn't care about SEI) by itself, it just reacts to an external signal. |
| Previous - 1 | 2 | 3 - Next |
