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2012-04-30 10:42

Flavioweb

Registered: Nov 2011
Posts: 463

Trig raster irq with sprites enabled.

This is the scenario:
- stable irq by raster polling + inverted cia timer
- sprites 3 to 7 enabled moving on y axis
- first value read from dc04 is $30
- irp triggered on no badline

i can stabilize irq correctly, without sprites, using a table of values 0-7 starting from offset $30 going backwards in table and reading these values accordingly with dc04 to set bpl branch offset.

I thougth that to compensate also sprites delay, i need to rebuild table considering also cycles fetched at line start by sprites data.
I calculated 3 cycles of BA setup + 2x4 cycles for sprite data = 11 cycles.
Rebuilt table with values $12 - 00, of course starting at offset $30 and added relative cmp #$c9 to adjust bpl targets with new values.

Still have perfect stable raster, but first opcode cycles after stabilization is executed forward or backward even spriter are on trigger line or not.

How can i do to correctly compensate cycles stoled by sprites?
What i'm missing?

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2014-09-18 07:34

lft

Registered: Jul 2007
Posts: 369

Don't know if you considered this already, but if the IRQ happens while the CPU is stalled (due to sprite fetch right at the rasterline switchover, can't remember if it's sprite 2 or 3 causing it), then the total latency is one cycle less than what you'd otherwise expect. It seems the 6510 performs the first step of IRQ processing (probably synchronising the signal) even though it is stalled.

2014-09-18 19:58

Flavioweb

Registered: Nov 2011
Posts: 463

Lft... interesting.
I suppose that the use of the word "halted", while the processor waits for the vic leave the bus free, don't mean really "stopped", but more likely, "waiting".
If "some strange" happens while CPU "wait", maybe -internally- something can be done.
Accordingly with
http://wiki.nesdev.com/w/index.php/CPU_interrupts
(IRQ and NMI tick-by-tick execution)
"1 PC R fetch opcode (and discard it - $00 (BRK) is forced into the opcode register instead)"
could be that "no real memory access" is done but, instead, some kind of "virtual bus access" that in fact it does not happen and "force" $00 into the opcode register.
At the same time the vic accessing the bus.
If my theory is correct, however, this should happen for every IRQ that happens during a badline/sprite fetch...

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