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gregg
Account closed
Registered: Apr 2005
Posts: 56 |
Some sort of multithreading.
About a week ago the topic multithreading came up on #c-64. So today I gave it a try. However, there's something wrong with my code and I can't really figure out what it is.
A short description: I have a fixed number of threads running and a CIA IRQ deals with context switching in a round-robin fashion. Every IRQ I save all current state data (SP, status register, PC, A, X, Y) in a structure and fetch the state data for the next thread.
In this example the first thread increments the screen background color (fast), while the second thread changes the border background color (slow). However the wait in the second thread runs too fast every other time, and I have no idea why. It's probably something wrong with the context switch stuff, maybe some of you could take a look at it?
Sources are for ACME.
!to "threading.prg",cbm
!cpu 6510
;!source "mylib.a"
!macro basic_header .a, .b, .c, .d {
*= $0801
!byte <.eol,>.eol,0,0,$9e
!text .a, .b, .c, .d
.eol: !byte 0,0,0
}
num_threads = 2
thread_num = $fd ; current thread number
;--------------------------------------------------------------------------
+basic_header "2", "0", "6", "1"
*= $080d
init: sei
; set up context switch IRQ
lda #$35
sta $01
lda #<context_switch
ldx #>context_switch
sta $fffe
stx $ffff
lda #0
sta thread_num
cli
jmp thread1
;--------------------------------------------------------------------------
context_switch:
pha
txa
pha
tya
pha
lda $dc0d
; save current thread
lda thread_num
; *8
asl
asl
asl
tay
; save A,X,Y
pla
sta thread_data+6,y
pla
sta thread_data+5,y
pla
sta thread_data+4,y
; save PSW
pla
sta thread_data+1,y
; save PC
pla
sta thread_data+2,y
pla
sta thread_data+3,y
; save SP
tsx
txa
sta thread_data,y
; next thread, wraparound
ldy thread_num
iny
cpy #num_threads
bne +
ldy #0
+ sty thread_num
; *8
tya
asl
asl
asl
tay
; restore thread data
; stack pointer first
lda thread_data,y
tax
txs
; push PC, PSW for RTI
lda thread_data+3,y
pha
lda thread_data+2,y
pha
lda thread_data+1,y
pha
; push registers
lda thread_data+6,y
pha
lda thread_data+5,y
pha
lda thread_data+4,y
pha
pla
tay
pla
tax
pla
rti
;--------------------------------------------------------------------------
thread1:
inc $d021
ldy #$02
jsr wait2
jmp thread1
thread2:
inc $d020
ldy #$80
jsr wait2
jmp thread2
wait2:
- ldx #0
dex
bne *-1
dey
bne -
rts
;--------------------------------------------------------------------------
thread_data:
!fill 8, 0
!byte $ff-$40, $22, <thread2, >thread2, 0,0,0,0
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Oswald
Registered: Apr 2002
Posts: 5094 |
Quote: You've not shown anything like that to be able to make such a claim.
I have quoted various sources upon what is multithreading. you have not. now rethink: who has the abilities to make such claims? |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: "In the context of this discussion the 6502 has two operating levels. One level is when it is executing an IRQ. The other not running an IRQ, we will call this the mainline."
read your definition again. how many times must I tell you the same thing? you cannot decide wether you are running irq or not, so u have no 2 op modes.
And again I will point you to post 85 which clarifies the situation and those terms as "IRQ mode and the mainline mode" and also "Also by setting or clearing the interrupt disable flag using SEI or CLI the code is actually causing he processor to switch between IRQ level to mainline operating level."
So like I have been saying you are wrong to keep on ignoring posts 80 and 85.
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: I have quoted various sources upon what is multithreading. you have not. now rethink: who has the abilities to make such claims?
You may have quoted the sources but your interpretation is flawed. |
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Oswald
Registered: Apr 2002
Posts: 5094 |
Quote: And again I will point you to post 85 which clarifies the situation and those terms as "IRQ mode and the mainline mode" and also "Also by setting or clearing the interrupt disable flag using SEI or CLI the code is actually causing he processor to switch between IRQ level to mainline operating level."
So like I have been saying you are wrong to keep on ignoring posts 80 and 85.
so lets see your post #80
"In the context of this discussion the 6502 has two operating levels. One level is when it is executing an IRQ. The other not running an IRQ, we will call this the mainline.
Pre-emptive multi-threading can use interrupts to switch between thread contexts so that when the interrupt finishes the mainline resumes execution from a different point."
irq mode = running an irq
mainline mode = not running an irq
its crystal clear. your own stupid definition. |
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Oswald
Registered: Apr 2002
Posts: 5094 |
Quote: You may have quoted the sources but your interpretation is flawed.
show me where. |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: so lets see your post #80
"In the context of this discussion the 6502 has two operating levels. One level is when it is executing an IRQ. The other not running an IRQ, we will call this the mainline.
Pre-emptive multi-threading can use interrupts to switch between thread contexts so that when the interrupt finishes the mainline resumes execution from a different point."
irq mode = running an irq
mainline mode = not running an irq
its crystal clear. your own stupid definition.
Again you are ignoring what was written in post 85.
The two operating levels are "IRQ mode and the mainline mode". This means "by setting or clearing the interrupt disable flag using SEI or CLI the code is actually causing he processor to switch between IRQ level to mainline operating level."
So you are wrong, again. |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: show me where.
For example when you keep on writing about privilege levels (post 96 is a good example), when it is irrelevant to this topic. |
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Oswald
Registered: Apr 2002
Posts: 5094 |
Quote: Again you are ignoring what was written in post 85.
The two operating levels are "IRQ mode and the mainline mode". This means "by setting or clearing the interrupt disable flag using SEI or CLI the code is actually causing he processor to switch between IRQ level to mainline operating level."
So you are wrong, again.
then decide for god's sake, post #80 or #85 should be taken from you seriously? they are defining operating levels differently. one saying it is running or not running an irq, the other its the state of the I flag.
which of #80 or #85 post should be taken as your definition then? and which of the rest of your posts is bullshitting and which one is not ? |
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Martin Piper
Registered: Nov 2007
Posts: 722 |
Quote: then decide for god's sake, post #80 or #85 should be taken from you seriously? they are defining operating levels differently. one saying it is running or not running an irq, the other its the state of the I flag.
which of #80 or #85 post should be taken as your definition then? and which of the rest of your posts is bullshitting and which one is not ?
It is very simple, you take both posts as part of my definition because post 85 follows on from post 80. Read post 80 first and then if you are still confused then you read post 85.
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Oswald
Registered: Apr 2002
Posts: 5094 |
your definition is flawed then. post #80 says the 2 modes are running or not running irq. post #85 says its about the I flag. in reality post #85 was just a reality skewer machine so you can save yourself being laughed at coz of the stupidity of pst #80. |
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