| |
Krill
Registered: Apr 2002
Posts: 2940 |
$D016 bit 5
There is this mysterious bit early on in the KERNAL reset routine:
FCEF: 8E 16 D0 STX $D016 ; VIC: Control Register 2 with X being anything in [0..5].
Now, some people [who?] claim that without this store to $d016, some [which?] cartridges won't start [citation needed].
However, $D016 apparently used to have a mysterious "reset bit" in supposedly early VIC-II revisions (those with only 5 not 9 luma steps, and then the early ones of those).
| Bit 5 | Reset-Bit: 1 = Stop VIC (no Video Out, no RAM |
| | refresh, no bus access) | Could this be the reason why some things on some machines (?) won't start without that store to $D016?
Do any machines still exist where setting $D016 to, say, $f8 would crash them (when running code from RAM)?
Or did this "reset bit" never exist? =) |
|
| |
chatGPZ
Registered: Dec 2001
Posts: 11290 |
AFAIK this bit is only needed/used in the VICII of the MAX Machine. If at all :) |
| |
Krill
Registered: Apr 2002
Posts: 2940 |
I thought so, too. And yet, seems to be a C-64 thing, too, after all. :) |
| |
chatGPZ
Registered: Dec 2001
Posts: 11290 |
I'd say: Proof or bullshit :) |
| |
Monte Carlos
Registered: Jun 2004
Posts: 355 |
What does "no ram" mean? How is d016 related to ram? |
| |
Jetboy
Registered: Jul 2006
Posts: 265 |
Quote: What does "no ram" mean? How is d016 related to ram?
VIC IS responsible for RAM refresh. Turning VIC off would mean no RAM refresh = mangled memory sooner than later. |
| |
Martin Piper
Registered: Nov 2007
Posts: 699 |
Quote: There is this mysterious bit early on in the KERNAL reset routine:
FCEF: 8E 16 D0 STX $D016 ; VIC: Control Register 2 with X being anything in [0..5].
Now, some people [who?] claim that without this store to $d016, some [which?] cartridges won't start [citation needed].
However, $D016 apparently used to have a mysterious "reset bit" in supposedly early VIC-II revisions (those with only 5 not 9 luma steps, and then the early ones of those).
| Bit 5 | Reset-Bit: 1 = Stop VIC (no Video Out, no RAM |
| | refresh, no bus access) | Could this be the reason why some things on some machines (?) won't start without that store to $D016?
Do any machines still exist where setting $D016 to, say, $f8 would crash them (when running code from RAM)?
Or did this "reset bit" never exist? =)
The stx $d016 at $fcef uses the X index result of the cartridge check routine at $fd02 which checks for the CBM80 being mapped into $8004, which is why some might think it is related to "cartridges won't start".
In reality, if a cartridge partially maps the CBM80, maybe the cartridge dump was bad or deliberately like that, then the screen would have a noticeable different X scroll during reset and mem test.
You can see the different screen X scroll during a soft reset if you do: > 8004 0 0 cd 38 30
And compare it with: > 8004 0 0 0 0 0
So it is probably just a visual debugging aid for auto-start cartridges. |
| |
Martin Piper
Registered: Nov 2007
Posts: 699 |
Although the programmer's reference guide does show d016 db5 as "RST" high. Hmm :)
The reset cartridge test at $fd02 does happen very early on after machine reset, the jsr does use the stack though. Hypothetically if the VIC defaults to being "in reset" and the memory refresh is off, this might mean the memory for the stack could fail... For the same/similar reason some machines fail with the VIC HSP using a "DMA delay" (DRAM refresh or whatever you want to call it) screen scroll.
Theoretically the delay between setting the stack memory, checking the cart, and reading the stack back with an rts could be small enough to not experience memory corruption.
This might explain why the $d016 set without "reset" is very early in the reset code, to make sure the VIC is refreshing memory...
All this would need to be tested if there are any VICs that do default to "reset on" and do not refresh the DRAM. |
| |
Martin Piper
Registered: Nov 2007
Posts: 699 |
Although the HSP/VSP DRAM issue does seem to be related to unexpected DRAM refresh signal timings, rather than lack of refresh timings. DRAM that isn't refreshed *at all* would tend to decay slower than badly refreshed DRAM due to signals flickering unexpectedly. |
| |
chatGPZ
Registered: Dec 2001
Posts: 11290 |
<offtopic>"VSP Bug" is not related to refresh - see LFTs article</offtopic> |
| |
Martin Piper
Registered: Nov 2007
Posts: 699 |
Quote: <offtopic>"VSP Bug" is not related to refresh - see LFTs article</offtopic>
Incorrect, see "In short, one memory cell gets refreshed with the bit value of a different memory cell." |
... 66 posts hidden. Click here to view all posts....
|
| Previous - 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 - Next |
