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Peiselulli
Registered: Oct 2006
Posts: 81 |
1541 low level programming problem
Hello,
I have a problem that I don't understand. I tried the
following code for the 1541 :
jsr $F97E ; MOTOR_ON
jsr $fe00 ; SET_READ_MODE
loop
BIT $1C00 ; SYNC signal
BMI loop ; not yet found?
LDA $1C01 ; read byte
lda $1c00
eor #$08
sta $1c00
CLV
-
bvc -
lda $1c01
jmp loop
I expect (if a floppy is inserted) that the LED flickers, but it does not. If I remove the "bvc" command, it works like expected. Has anybody a idea what I have forgotten to initialize ?
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Conrad
Registered: Nov 2006
Posts: 849 |
Try this code. It isn't modified, it's just some of the code is re-arranged:
jsr $F97E ; MOTOR_ON
jsr $fe00 ; SET_READ_MODE
loop
BIT $1C00 ; SYNC signal
BMI loop ; not yet found?
bvc *
lda $1c01
clv
lda $1c00
eor #$08
sta $1c00
jmp loop
Bear in mind that the process is very fast so you'll probably see very faint flicker in the drive LED, which means it's working.
I'm not too sure what the difference is, but I think it's something to do with clearing the overflow flag at the right point. |
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Peiselulli
Registered: Oct 2006
Posts: 81 |
many thanks, now it works
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Frantic
Registered: Mar 2003
Posts: 1648 |
Edit: [nothing.] :) |
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Peiselulli
Registered: Oct 2006
Posts: 81 |
Hmm, strange things happens:
If I modify the Code like this to read a second byte:
jsr $F97E ; MOTOR_ON
jsr $fe00 ; SET_READ_MODE
loop
BIT $1C00 ; SYNC signal
BMI loop ; not yet found?
bvc *
lda $1c01
clv
bvc *
lda $1c01
clv
; short break to see the LED flickering
ldy #$20
ldx #$00
-
inx
bne -
dey
bne -
lda $1c00
eor #$08
sta $1c00
jmp loop
It did not work any more.
Any suggestions ?
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Krill
Registered: Apr 2002
Posts: 2980 |
This is from my loader:
waitsync: bit VIA2_T1C_H
bpl wsynctmout
bit VIA2_PRB
bmi waitsync
bit VIA2_PRA
clv
bvc *
ldx #$00
lda VIA2_PRA; is never $00 but usually $52/$55
clv
rts
It's pretty long ago, but i guess the read access to $1c01 (VIA2_PRA) after the sync and _before_ the first clv is mandatory for some reason.
May i ask what your experiments will eventually lead to? :) |
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Krill
Registered: Apr 2002
Posts: 2980 |
(Excuse my lame posting skillz)
This is from my loader:
waitsync: bit VIA2_T1C_H
bpl wsynctmout
bit VIA2_PRB
bmi waitsync
bit VIA2_PRA
clv
bvc *
ldx #$00
lda VIA2_PRA; is never $00 but usually $52 (header) or $55 (data)
clv
rts
It's pretty long ago, but i guess the read access to $1c01 (VIA2_PRA) after the sync and _before_ the first clv is mandatory for some reason.
May i ask what your experiments will eventually lead to? :) |
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Peiselulli
Registered: Oct 2006
Posts: 81 |
this experiments have no real aim, its just for getting more knowledge programming the 1541.
But the thing getting even more strange:
The following code did not work, but I see no really difference to your code:
loop
BIT $1C00 ; SYNC signal
bmi loop ; not yet found?
bit $1c01
clv
bvc *
lda $1c01
clv
ldy #$20
ldx #$00
-
inx
bne -
dey
bne -
lda $1c00
eor #$08
sta $1c00
jmp loop
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Krill
Registered: Apr 2002
Posts: 2980 |
Have you executed an SEI and are you really on a 1541 (and not a 1571 in 2mhz mode or so)? |
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Peiselulli
Registered: Oct 2006
Posts: 81 |
I am on a 1541-II and i have do a "sei" before.
I have the feeling that anything is missing for reading bytes
(because the sync bit works in write mode, too)
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Krill
Registered: Apr 2002
Posts: 2980 |
Hmm, if you're on a valid formatted track i don't see a reason for the routine to fail. It's stuck in the bvc loop, right? |
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