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TWW
Registered: Jul 2009
Posts: 545 |
Regarding Interrupts
I have some hypothetical questions regarding IRQ interrupts;
#1: If an IRQ event is pulsed (IRQ line pulled low) for a duration of 3-4 cycles and this happens during a 6-7 cycle instruction, can the IRQ be missed by the MPU?
#2: Are the IRQ-flags handled by the MPU or the chips in question (CIA#1/VICII) (I suspect the VIC/CIA)?
#3: If the answer to #1 is yes & #2 is CIA/VIC, would a "missed IRQ" still be flagged?
#4: If an IRQ remains unacknowledged will the latent IRQ event retrigger a interrupt on the CPU after an RTI?
#4.5 I have tested #4 and found it to re-trigger after 6 cycles. Can someone confirm and why 6 cycles?
#5: The interrupt initialization takes 7 cycles wheras the 2 first cycles are described as "internal functions" in a 6502 diagram I saw. What exactly is going on during these 2 clock cycles?
#6: If you ack CIA#1 with a LDA $dc0d, this operation takes 4 cycles. In whihc cycle does the flag(s) actually clear?
#7: Same as #6 just with LDA #$ff, STA $d019.
If there is some documentation around this I would be gratefull for some pointers. And yes I know some of these things could probably be tested and figgured out but hey what's a forum for^^ |
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
Quoting TWWI have some hypothetical questions regarding IRQ interrupts;
#1: If an IRQ event is pulsed (IRQ line pulled low) for a duration of 3-4 cycles and this happens during a 6-7 cycle instruction, can the IRQ be missed by the MPU?
No, VIC/CIA will have their IRQ flags set until the CPU acknowledges them.
Quote:#2: Are the IRQ-flags handled by the MPU or the chips in question (CIA#1/VICII) (I suspect the VIC/CIA)?
VIC/CIA, then logically OR'ed into the CPU.
Quote:#3: If the answer to #1 is yes & #2 is CIA/VIC, would a "missed IRQ" still be flagged?
There is no "missed IRQs", since the CPU has to acknowledge IRQs.
Quote:#4: If an IRQ remains unacknowledged will the latent IRQ event retrigger a interrupt on the CPU after an RTI?
Yes.
Quote:#4.5 I have tested #4 and found it to re-trigger after 6 cycles. Can someone confirm and why 6 cycles?
RTI = 6 cycles.
Quote:#5: The interrupt initialization takes 7 cycles wheras the 2 first cycles are described as "internal functions" in a 6502 diagram I saw. What exactly is going on during these 2 clock cycles?
Probably fetching the next opcode + discarding the opcode and feed a BRK-like internal instruction.
Quote:#6: If you ack CIA#1 with a LDA $dc0d, this operation takes 4 cycles. In whihc cycle does the flag(s) actually clear?
The last one ofcourse. The previous cycles are needed to fetch the 3 bytes of the opcode itself.
Quote:#7: Same as #6 just with LDA #$ff, STA $d019.
same.
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Fresh
Registered: Jan 2005
Posts: 101 |
#1 IRQ lines are usually kept down until MPU ack them. So they usually last more then 3/4 cycles. I've not read anything about that but to me it makes sense that MPU loses such an IRQ as I think the line is not buffered and it is read only in specific cycles. Problem is you can't create such an IRQ with CIA or VIC.
#2 IRQ flags are handled by peripherals. MPU can only mask (don't care) the IRQ line but if something generates an IRQ while IRQ is masked out, the mpu will serve it as soon as you unmask it.
#3 Can't answer: IMHO VIC & CIA can't generate such a pulse-like IRQ.
#4 Read answer #2
#4.5 I guess it depends on RTI duration
#5
1 PC R fetch opcode, increment PC
2 PC R read next instruction byte (and throw it away), increment PC
3 $0100,S W push PCH on stack (with B flag zero), decrement S
4 $0100,S W push PCL on stack, decrement S
5 $0100,S W push P on stack, decrement S
6 $FFFE R fetch PCL
7 $FFFF R fetch PCH
Source: http://codebase64.org/doku.php?id=base:6510_instruction_timing
#6 the last cycle read the value so I *think* it should clear instantly the flag
#7 same as #6, write happens on fourth cycle
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TWW
Registered: Jul 2009
Posts: 545 |
Very nice. Thanx both of you.
Regarding the IRQ pulse stuff I read this somewhere(?) regarding IRQs triggering on low signal instead of high to low state (like the NMI). The theory was if the IRQ isn't kept low long enough for the current Instruction to complete executing the MPU would miss it.
However based on both your statements has to be wrong since the CIA/VIC (N)OR's it's IRQ flags onto the IRQ line.
How would this work regarding an external event from the expansionport f.ex. (If you push the freeze button really fast :-D)? |
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Fresh
Registered: Jan 2005
Posts: 101 |
Should you have the fastest finger of the world and make a pulse of... say... 3 cycles, you may definetely miss the IRQ: afaik the line is checked during last cycle of each instruction so, with the longest of them (6/7 cycles), if the pulse fall just 1-2 cycles after decoding, it will be too late for that instruction and it will end too soon for the next one. Imho It shouldn't be catched. |
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daison
Registered: May 2005
Posts: 90 |
Quote: Should you have the fastest finger of the world and make a pulse of... say... 3 cycles, you may definetely miss the IRQ: afaik the line is checked during last cycle of each instruction so, with the longest of them (6/7 cycles), if the pulse fall just 1-2 cycles after decoding, it will be too late for that instruction and it will end too soon for the next one. Imho It shouldn't be catched.
The ladies would love you instantly though =P |
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Fresh
Registered: Jan 2005
Posts: 101 |
Guess it's a bit too fast even for them; and then there won't be any fun having her reaching climax in less than a second. |
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tlr
Registered: Sep 2003
Posts: 1790 |
Quote: Should you have the fastest finger of the world and make a pulse of... say... 3 cycles, you may definetely miss the IRQ: afaik the line is checked during last cycle of each instruction so, with the longest of them (6/7 cycles), if the pulse fall just 1-2 cycles after decoding, it will be too late for that instruction and it will end too soon for the next one. Imho It shouldn't be catched.
I guess this could be verified by acking the interrupt just when it is about to happen.
1. Start a timer that will trigger an IRQ.
2. wait using nops until around the time the IRQ should trigger.
3. perform an ack of the timer IRQ such that the IRQ is about to happen during the instruction doing the ACK.
4. profit!
Here you can experiment with different kinds of acks, e.g Read or RMW, to get the ack to happen at different parts of the instruction execution.
If it is adapted to using VIC-II interrupts a Store instruction can be used to ack. |
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Fresh
Registered: Jan 2005
Posts: 101 |
This is just a (very!!) ugly code I've made up in a few minutes, I've tested it on Winvice 2.2. It would make sense to try it on a real machine.
Anyway, it looks like it's not possible to avoid an IRQ.
IRQ not fired: short white line
IRQ fired: long coloured (possibly white) line
rastline = $20 ;
*=$0801
word eoprg
word 2010
byte $9E,[intro]d,":",$8f,$20,"IRQ TEST"
byte 0
eoprg
word 0
intro
sei
jsr initIRQ
cli
jmp *
fstirq ; Line $20
pha
txa
pha
tya
pha
dec $fffd
inc $fffd
nop
nop
lsr $d019
inc $d012
lda #<secirq
sta $fffe
cli
nop
nop
nop
nop
nop
nop
brk
secirq ; Line $21
lsr $d019
lda #<thdirq
sta $fffe
dec $fffd
dec $fffd
inc $fffd
dec $fffd
inc $fffd
dec $fffd
lda #$21
eor $d012
beq synced ;+3
synced ; Synced - line $22
lda #$23 ; 2 -5
sta $d012 ; 4 -9
cli ; 2 -11
ldx #$00 ; 2 -13
sta $fffd ; 4 -17
dec $fffd ; 6 -23
inc $fffd ; 6 -29
inc $fffd ; 6 -35
dec $fffd ; 6 -41
inc $fffd ; 6 -47
dec $fffd ; 6 -53
; Choose how many cycle you need to wait by commenting/uncommenting (4-12)
; - ww IRQ - When?
;inc $ff ;
;inc $f500,x ; - 12 Yes - Before DEC
;sta $fffd ;
;inc $f500,x ; - 11 Yes - After DEC
;sta $fffd ;
;inc $f500 ; - 10 Yes - After DEC
;sta $fffd ;
;inc $f5 ; - 9 Yes - After DEC
;sta $fffd ;
;sta $fffd ; - 8 Yes - After DEC
;inc $f500,x ; - 7 Yes - After DEC
;inc $fffd ; - 6 Yes - After DEC
;inc $ff ; - 5 No
sta $fffd ; - 4 No
dec $d019,x
inc $fffd
inc $fffd
inc $d020
dec $d020
lsr $d019
end
pla
pla
pla
lda #rastline
sta $d012
lsr $d019
lda #<fstirq
sta $fffe
pla
tay
pla
tax
pla
rti
thdirq
tsx
inx
inx
lda $0100,x
sta $fe
sta $d020
pla
pla
pla
lda #$00
sta $d020
jmp end
initIRQ
sei
lda #$35
sta $01
lda #$7f
sta $dc0d
sta $dd0d
lda $dc0d
lda $dd0d
lda #$00
sta $d020
sta $d011
lda #rastline
sta $d012
lda #<fstirq
sta $fffe
lda #>fstirq
sta $ffff
lda #$01
sta $d01a
lsr $d019
rts
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
On a flat C128 I get a short (6 cycles) white line.
EDIT: On C64 too. |
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Fresh
Registered: Jan 2005
Posts: 101 |
Sorry Graham, I didn't say that there are some line to comment/uncomment inside the code to do a real test.
The code as is doesn't interrupt because IRQ happens after DEC.
Look inside the code, instead of 4 cycles uncomment 9 cycles.
Anyway I think that CIA IRQ can give better results as acknowledge may be done before last instruction cycle (it only needs a read). |
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