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MRT
Account closed
Registered: Sep 2005
Posts: 149 |
2 bit irq loader
Hmm, just a question...
Is there a 2 bit irq loader, which doesn't require blocking other interrupts while loading a byte?
i.o.w. Is there a realy fast irq loader which doesn't block any interrupts and let me use my beloved sprites? :-)
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MagerValp
Registered: Dec 2001
Posts: 1078 |
Quote: K, I've got a message from Dahl, telling me that the bits get inverted. So I checked a little, and found the following table...
|DC|DC|DC|DC|
-----+--+--+--+--+
$1800|11|01|10|00|
-----+--+--+--+--+
$dd00|00|01|10|00|
-----+--+--+--+--+
In other words, only when setting both lines to low or high, they get inverted. But when one sets only 1 line high or low, the lines won't get inverted.
Is this correct?
No. They are always inverted. Have you setup $dd02 correctly?
Also, you can use BIT $1800 when waiting, for less jitter.
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MRT
Account closed
Registered: Sep 2005
Posts: 149 |
Hmm, didn't set the data direction registers coz I thought the default setting should be good. The both out-lines are enabled on both sides by default. But, I forgot to check if they were still correct when I made the table above... :-S
I'll check it again. :-)
bout that bit $1800...
You cannot use it when you want to check if both lines are high, can you? Then you check if at least one of the two lines (or both) is high.
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ChristopherJam
Registered: Aug 2004
Posts: 1409 |
@MRT - are you sure you didn't get clock and data the wrong way around on either your reads or your writes? That would explain the seeming lack of inversion when they are different to each other :)
err, but not the 00. I'll go get some coffee now :-P |
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Krill
Registered: Apr 2002
Posts: 2980 |
MRT: The bit instruction is to and what cmp is to sbc, more or less. It does mainly the same, just that your registers aren't altered, instead only the flags. So if the Z-flag is set after the bit instruction, both lines are low, if not, directly branch to the bit opcode again.
And that table seems b0rked. :)
Oh, and i just made a new version of my loader, still interesed, MRT? |
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MRT
Account closed
Registered: Sep 2005
Posts: 149 |
@ChristopherJam:
poor me some too ;-)
@Krill:
He he, I know how bit works :)
Just saying you can use it only to check if all is low or all is not low.
And hell yeah... I'm interrested!
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Ninja
Registered: Jan 2002
Posts: 411 |
Quote: Yes it is. But since the 1541 is the least common denominator, all other drive types don't really have to be faster, at least for demos. And i'd always prefer more compatibility over more speed. :)
Really? Now, that's good news >:-> |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: @ChristopherJam:
poor me some too ;-)
@Krill:
He he, I know how bit works :)
Just saying you can use it only to check if all is low or all is not low.
And hell yeah... I'm interrested!
@MRT: BIT conviniently copies bit 6 and 7 to the N and V flags. Hence:
lda #$c0
bit $dd00
beq data_and_clock_low
bvc data_low
bvs data_hi
bmi clock_low
bpl clock_hi
I might have mixed up data and clock ofcourse...
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MRT
Account closed
Registered: Sep 2005
Posts: 149 |
Quote: @MRT: BIT conviniently copies bit 6 and 7 to the N and V flags. Hence:
lda #$c0
bit $dd00
beq data_and_clock_low
bvc data_low
bvs data_hi
bmi clock_low
bpl clock_hi
I might have mixed up data and clock ofcourse...
I understand the bit opcode, but when scanning for both bit set, I don't think your code is cheaper then the code below? ;wait for both lines high
lda #%11000000
and $dd00
cmp #%11000000
bne *-7
When both bits are set I use 10 cc. When both bits are set in your example it would also take 10 cc, when I take the shortest path (see code below) ;wait for both lines high
lda #%11000000
bit $dd00
bvc *-3
bmi *-5
The difference here is thet your code is faster when both bits aren't set. But... You can only do this for $dd00 and not for $1800, and your code will have a different timing for each different pair of bits.
I'm writing a loader which is partly time-based, so I need to have stable timing. |
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j0x
Registered: Mar 2004
Posts: 215 |
MRT: It's not necessary to load the accumulator when only using the N and V flags
How about this one (assuming you want to do what your first code snippet does, not the second):
lda #$bf
cmp $dd00
bcs *-3
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Krill
Registered: Apr 2002
Posts: 2980 |
MRT: how stable? Bit+branch still gives you at least 7 cycles jitter. For less jitter, you need to apply a technique known from stable rasters, called half variance. But you only need that if you don't handshake/sync for many many cycles. |
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