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Testa
Account closed
Registered: Oct 2004
Posts: 197 |
fetch the 0-sprite. with open borders...
hi,
ik have a little problem.. i want to open the sideborders with the 4 lowest sprites... i have two questions about it..
when i do the D016 write i use a dec d016 or a lsr or ror as opcode... why does a sty, sta, stx not work....
has it something to do with cpu takeover cycles at that point...
second question... what to do on a badline....
there are not enough free cycles. with 4 sprites for a inc, ror or lsr d016 instead of a sta, sty or stx...
i realize it is common knowledge.. but sorry i dont. know it...
bye...
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Flavioweb
Registered: Nov 2011
Posts: 463 |
I tought that is a way to use sprite 0 (almost in pal) and open side border with a badline, but it's from top of my mind, so not tested or coded yet.
Sprite zero is fetched at cycle 59, with a takeover of three cycles before it.
Looking at vic article scheme for a badline where sprite zero is enabled, we can see that at cycle 55 BA is up.
That said, in the first part of a badline, BA stay up until cycle 12.
If we have a stable raster routine, via CIA timing that let us to stat a LDA/STA at cycle 8 of a line, we can do an lda #$xx/STA $D016 ending with cycle 3 of STA (last read cycle) on cycle 12 of the badline.
So, cpu is halted here, leaving the write cycle to be executed during the cycle 55 of the badline, theoretically opening the border.
Then we have all time to restore $D016 value as needed.
From the top of my mind... of course.
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Copyfault
Registered: Dec 2001
Posts: 478 |
@Flavioweb: nice idea, but it won't work because also the read cycle causing the cpu to halt is postponed, i.e. there's always a read cycle before any write cycle.
You suggest to shift the 3rd cycle of the STA to cycle 12 of a BL. By doing this, the read cycle of the STA is NOT processed at cycle 12, but (if we stick to your example with only sprite 0 turned on) at cycle 60 of the very same rl. The write cycle of the STA follows at cycle 61. Unfortunatly, this is to late for opening the sideborder :( |
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Flavioweb
Registered: Nov 2011
Posts: 463 |
Quoting CopyfaultYou suggest to shift the 3rd cycle of the STA to cycle 12 of a BL. By doing this, the read cycle of the STA is NOT processed at cycle 12, but (if we stick to your example with only sprite 0 turned on) at cycle 60 of the very same rl. The write cycle of the STA follows at cycle 61. Unfortunatly, this is to late for opening the sideborder :(
Ok, maybe that processor is halted BEFORE last read cycle then, last read cycle and write cycle of STA are postponed to cycle 55 of the line.
Here we have cycle 55 with BA up, then 3 cycle of takeover (BA low), then 2 cycle to fetch sprite zero.
Since processor can't be halted during write operations, could not be that we have -read cycle of STA at cycle 55 of the line- and -write cycle of STA at cycle 56 of the line-?
This would work, or not? |
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Fresh
Registered: Jan 2005
Posts: 101 |
This only applies on NTSC vics (6567); PAL vics (6569) haven't got 'free' cycles between badline and sprite 0 fetch: BA stays low from cycle 12 to 59, so the cpu stops somewhere in cycles 12-14 and restarts at 60. |
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Flavioweb
Registered: Nov 2011
Posts: 463 |
In this demo:
In the Border We Trust
there are 8 sprites and no border at all... |
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Mr. SID
Registered: Jan 2003
Posts: 424 |
No bad lines in that one... |
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