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Krill
Registered: Apr 2002
Posts: 2980 |
TIL: The instruction after SEI can be executed before a pending IRQ is handled
As described here: http://visual6502.org/wiki/index.php?title=6502_Timing_of_Inter..
I never knew this, after all those years, and thought i'd share this as a heads-up.
Thanks to Bubis for pointing it out to me! |
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TWW
Registered: Jul 2009
Posts: 545 |
Ok, that was perhaps a bit much... sorry... lolz |
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Krill
Registered: Apr 2002
Posts: 2980 |
Quoting spider-jNo need for $d019 in this case, is that correct? If you scroll up a bit to some of MagerValps comments:
Quoting MagerValpClearing pending IRQs with $d019 is not strictly necessary if you run from a freshly reset machine (the kernal writes $0f to $d019 on reset), but if something else ran before and exited to the basic prompt there may be an unacknowledged raster IRQ pending. [...] Hmm, I wonder if the soft reset before the ready prompt clears it... Just checked, and afaict, nope. [...] Clearing $d019 is necessary, and testing a bit more it seems like it's necessary even on a freshly reset machine. |
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spider-j
Registered: Oct 2004
Posts: 498 |
Quoting KrillIf you scroll up a bit to some of MagerValps comments:
Ah okay, saw his code example also now. Didn't see that earlier. That probably happens when you're half-assed reading csdb threads while working... Thx. |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
"Clearing $d019 is necessary, and testing a bit more it seems like it's necessary even on a freshly reset machine."
could you provide a testcase for this? sounds like something that should be checked if it behaves the same in VICE :) |
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Copyfault
Registered: Dec 2001
Posts: 478 |
Quoting KrillQuoting CopyfaultIs it possible to have an IRQ execution directly after the write cycle of that STA $D019? [...] (has influence on the irq code, i.e. wether an INC $01 at the beginning suffices or a LDA#$35:STA$01 is a must You ack a possibly pending raster IRQ with the write access to $d019, but any potentially arising subsequent raster IRQ condition should not trigger an actual IRQ before you enable the raster IRQs via $d01a. This will be when you have already set up your IRQ handler, and that one will behave and properly backup and restore $01. So i guess INC $01 works.
So true! Sorry for my confusion, but actually I meant $D01A, not $D019. So, now hopefully the correct question: can a raster IRQ be triggered directly after writing to $D01A? My understanding would be that even if an IRQ condition is active directly after the $D01A-write, the IRQ routine should not be processed before the next instruction has been finished. So my assumption is as follows:
...
lda #$01
sta $d01a
-> irq condition here... <-
dec $01
-> ...is processed here <-
(so INC $01 at the beginning of the IRQ code would suffice)
Is this correct? |
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MagerValp
Registered: Dec 2001
Posts: 1078 |
The VIC will register a pending raster IRQ whenever it reaches the raster line specified in $d011/12, regardless of the state of $d01a. So yes, when you enable $d01a, unless you cleared $d019 just before, you will trigger a raster IRQ before the next instruction.
It's easy to demonstrate using the VICE monitor:
(C:$0218) > d011 9b ff ; Set IRQ line to 511, i.e. never
(C:$0218) > d019 ff 00 ; Disable VIC IRQs and clear pending
(C:$0218) x ; Run for a couple of frames
(C:$ea7e) m d019 d01a ; Verify that no IRQ has been latched
>C:d019 70 f0
(C:$d0a9) > d011 1b ; Set IRQ line to 255
(C:$d0a9) x ; Run for a couple of frames
(C:$021a) m d019 d01a ; Verify that a raster IRQ has been latched
>C:d019 71 f0
(C:$0216) z ; Step one instruction, we're in keyboard polling
.C:0218 85 CC STA $CC - A:00 X:FF Y:2E SP:f2 ..-...ZC 2515975
(C:$0218) > d01a 01 ; Enable raster IRQ
(C:$0218) z ; Next instruction is IRQ handler
.C:ff48 48 PHA - A:00 X:FF Y:2E SP:ef ..-..IZC 2515985
So, just ignore my previous speculation about $d019 (I should have tested before posting :) and use the IRQ setup routine from comment #26. |
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Krill
Registered: Apr 2002
Posts: 2980 |
Are we certain that VICE works correctly there? Things like various cycle delays and internal pipelining aren't perfect yet, afaik, hence groepaz asking for test programs whenever possible. :) |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
indeed, especially how registers behave after powerup and/or reset is always questionable, because its documented rather poorly (if at all). |
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Oswald
Registered: Apr 2002
Posts: 5094 |
nice, didnt know that d019 is almost always on, nice insight. |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
btw, i wouldnt trust the VICE monitor to do such testing even IF the implementation in VICE is generally correct - the sideeffects (like clearing latches when reading) may or may not behave as expected. better make a small test program and verify it on a real c64. |
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