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Forums > C64 Coding > Some sort of multithreading.

2008-04-08 22:51

gregg
Account closed

Registered: Apr 2005
Posts: 56

Some sort of multithreading.

About a week ago the topic multithreading came up on #c-64. So today I gave it a try. However, there's something wrong with my code and I can't really figure out what it is.

A short description: I have a fixed number of threads running and a CIA IRQ deals with context switching in a round-robin fashion. Every IRQ I save all current state data (SP, status register, PC, A, X, Y) in a structure and fetch the state data for the next thread.

In this example the first thread increments the screen background color (fast), while the second thread changes the border background color (slow). However the wait in the second thread runs too fast every other time, and I have no idea why. It's probably something wrong with the context switch stuff, maybe some of you could take a look at it?

Sources are for ACME.

!to "threading.prg",cbm
!cpu 6510
;!source "mylib.a"
!macro basic_header .a, .b, .c, .d {
        *= $0801
        !byte <.eol,>.eol,0,0,$9e
        !text .a, .b, .c, .d
.eol:   !byte 0,0,0
}

num_threads = 2
thread_num = $fd		; current thread number

;--------------------------------------------------------------------------
+basic_header "2", "0", "6", "1"

*= $080d

init:	sei
		; set up context switch IRQ
		lda #$35
		sta $01

		lda #<context_switch
		ldx #>context_switch
		sta $fffe
		stx $ffff
		
		lda #0
		sta thread_num

		cli
		jmp thread1

;--------------------------------------------------------------------------
context_switch:
		pha
		txa
		pha
		tya
		pha
		lda $dc0d

		; save current thread
		lda thread_num
		; *8
		asl
		asl
		asl
		tay
		; save A,X,Y
		pla
		sta thread_data+6,y
		pla
		sta thread_data+5,y
		pla
		sta thread_data+4,y
		; save PSW
		pla
		sta thread_data+1,y
		; save PC
		pla
		sta thread_data+2,y
		pla
		sta thread_data+3,y
		; save SP
		tsx
		txa
		sta thread_data,y

		; next thread, wraparound
		ldy thread_num
		iny
		cpy #num_threads
		bne +
		ldy #0
+		sty thread_num

		; *8
		tya
		asl
		asl
		asl
		tay

		; restore thread data
		; stack pointer first
		lda thread_data,y
		tax
		txs
		; push PC, PSW for RTI
		lda thread_data+3,y
		pha
		lda thread_data+2,y
		pha
		lda thread_data+1,y
		pha
		; push registers
		lda thread_data+6,y
		pha
		lda thread_data+5,y
		pha
		lda thread_data+4,y
		pha

		pla
		tay
		pla
		tax
		pla
		rti
	
;--------------------------------------------------------------------------
thread1:
		inc $d021
		ldy #$02
		jsr wait2
		jmp thread1


thread2:
		inc $d020
		ldy #$80
		jsr wait2
		jmp thread2
		
wait2:
-		ldx #0
		dex
		bne *-1
		dey
		bne -
		rts

;--------------------------------------------------------------------------
thread_data:
	!fill 8, 0
	!byte $ff-$40, $22, <thread2, >thread2, 0,0,0,0

... 211 posts hidden. Click here to view all posts....

2008-04-14 16:38

chatGPZ

Registered: Dec 2001
Posts: 11154

Quote:

Code cannot tell if it was called because of an interrupt or because of a jsr or a jmp.

cant you check the cpu status on the stack? :)

2008-04-14 16:44

trident

Registered: May 2002
Posts: 81

Quote: Quote:

Code cannot tell if it was called because of an interrupt or because of a jsr or a jmp.

cant you check the cpu status on the stack? :)

Yeah, but how do you know if it really is a pushed status byte or just some random data that happens to look like a status byte?

2008-04-14 17:13

chatGPZ

Registered: Dec 2001
Posts: 11154

by pushing the status yourself?

2008-04-14 21:23

Martin Piper

Registered: Nov 2007
Posts: 647

Quote: No, the 6502 does not have two operating levels. There is no difference between machine code instructions that are executed because of an interrupt (i.e., an IRQ handler) and those that are executed because of a reset (i.e., the main code). Code cannot tell if it was called because of an interrupt or because of a jsr or a jmp.

You are wrong, the 6502 does have two operating levels, in the context of this subject. IRQ mode and the mainline mode. It's part of the status register. Note we are not mentioning the NMI here but that also interrupts the IRQ and mainline mode. The IRQ in the 6502 is level triggered and the NMI is edge triggered. There is a difference between instructions executed in IRQ mode and mainline mode. Between each instruction executed in IRQ mode there will not be any interruption by another IRQ whereas in mainline mode between each instruction the code can be interrupted. This fact is used by some multi-threading routines to get the context switch to work.
There is also a difference between code executed at reset time and that of IRQs. The reset forces the IRQ disable bit to be set which means the CPU ignores any IRQ request until the bit is cleared, of course.

It doesn't matter if code cannot tell where it was called from, this is what is known as a straw man logical fallacy, because the detection of the "source of execution" is irrelevant to being able to have an IRQ alter where the CPU resumes operation of mainline mode. My point made earlier still stands as being completely correct.

Also by setting or clearing the interrupt disable flag using SEI or CLI the code is actually causing he processor to switch between IRQ level to mainline operating level.

We can, for example, be in an IRQ, as part of the code we can use CLI followed by a series of NOPs which could then allow another IRQ to run again. This method is called a double IRQ which is useful for certain graphical tricks.

Then lets not forget the BRK instruction. On some 6502s if an NMI hits at the same time as a BRK then the BRK interrupt won't get executed. This bug highlights the operating level changes the CPU does internally.

Also in some 6502s there is a wait instruction, called WAI, which ensures that the processor is not in the middle of an instruction for when an IRQ needs to be services. This gets rid of the latency from signalling the IEQ nd the IRQ starting to be executed. This again highlights the internal operating level changes of the 6502.

2008-04-15 06:17

Oswald

Registered: Apr 2002
Posts: 5032

thats the biggest bullshit even in this topic I have read so far :D

WP:

"CPU modes (also called processor modes or CPU privilege levels, and by other names) are operating modes for the central processing unit of some computer architectures that place restrictions on the operations that can be performed by the process currently running in the CPU."

"At a minimum, any CPU with this type of architecture will support at least two distinct operating modes, and at least one of the modes will provide completely unrestricted operation of the CPU.

...

In kernel mode, the CPU may perform any operation provided for by its architecture. Any instruction may be executed, any I/O operation may be initiated, any area of memory may be accessed, and so on. In the other CPU modes, certain restrictions on CPU operations are enforced by the hardware. Typically certain instructions are not permitted, I/O operations may not be initiated, some areas of memory cannot be accessed etc. Usually the user-mode capabilities of the CPU are a subset of the kernel mode capabilities, but in some cases (such as hardware emulation of non-native architectures), they may be significantly different from kernel capabilities, and not just a subset of them.

At least one user mode is always defined, but some CPU architectures support multiple user modes, often with a hierarchy of privileges."

2008-04-15 08:35

Martin Piper

Registered: Nov 2007
Posts: 647

You are wrong and you are also using a straw man logical fallacy because I didn't write "privilege levels" I actually wrote "operating levels". When you use a straw man logical fallacy what you are doing is incorrectly restating a position into soemthing that is easily shown to be false and then refuting it, when actually you are not refuting the real position as stated.

The two terms are subtly different. *If* I had meant privilege levels I would have written it.
The 6502 has IRQ mode and non-IRQ mode operating levels, it is obvious and cannot be refuted since it is a fact.

2008-04-15 08:43

Stryyker

Registered: Dec 2001
Posts: 465

Martin: I disagree with your comment about differents between code in main and IRQ modes and interrupts being generated. You have already stated interrupts can occur during IRQ - double interrupts often used for stable stable rasters.

2008-04-15 08:50

chatGPZ

Registered: Dec 2001
Posts: 11154

check again how 6502 works (in this case, differently than most other cpus), you can't fire another irq when the cpu is in irq mode :)

2008-04-15 08:50

Martin Piper

Registered: Nov 2007
Posts: 647

Quote: Martin: I disagree with your comment about differents between code in main and IRQ modes and interrupts being generated. You have already stated interrupts can occur during IRQ - double interrupts often used for stable stable rasters.

No, read what I posted again. What actually happens in the double IRQ example I gave is that whatever is running in the mainline mode is interrupted by the IRQ. This sets the interrupt disable flag in the status. Then while running in IRQ mode the code executes "CLI followed by a series of NOPs which could then allow another IRQ to run again". By executing CLI the processor is switched from "not allowing IRQs mode" to "allowing IRQs mode". i.e. IRQ mode to mainline mode.

In effect using SEI puts the CPU in "not allowing IRQs mode" which is as we have termed it is "IRQ mode" for brevity.

2008-04-15 08:57

Oswald

Registered: Apr 2002
Posts: 5032

yeah, actually there arent just mainline and irq mode, there is carry set mode, overflow bit set mode, brk flag set mode, z flag set mode etc. count them yourself. the 6510 is actually like todays superscalar cpus. it can do multithreading, and verious privilige hierarchis, everything :D

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