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oleoleo2
Account closed
Registered: Oct 2008
Posts: 21 |
Simple interrupt question.
HI Guys.
I am new to programming in assembler/machinecode on the c64. I have a simple question about the registers $DC0D and $DD0D. I can see in a lot of small programming-examples that they're set to the value $#7F (= 01111111), but none with deep explanations. I found this:
DC0D
CIA Interrupt Control Register (Read IRQs/Write Mask)
7 IRQ Flag (1 = IRQ Occurred) / Set-Clear Flag
4 FLAG1 IRQ (Cassette Read / Serial Bus SRQ Input)
3 Serial Port Interrupt
2 Time-of-Day Clock Alarm Interrupt
1 Timer B Interrupt
0 Timer A Interrupt
'Masking' would say that you define what the computer should look at what to not to look at right? The example where I have seen $DC0D is set to $#7F is where the raster-interrupt routine is used. Does the = 1 mean that bit 0-4 is not used and if that is so, then why is the bits 'inverted'? I guess the bit 0-4 is what we not wan't when using raster-interrupt?
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
$7f is bit7=0, all other bits=1 ... so the "set-clear flag" is 0, meaning "clear". all other bits are 1, so storing $7f to dc0d/dd0d clears all bits in the irq mask, meaning all irqs from that cia are disabled (and thats what you usually want when doing a raster irq) |
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oleoleo2
Account closed
Registered: Oct 2008
Posts: 21 |
Thanks for the reply!
Yes bit 7 makes sense, but what I don't understand is: isn't setting all the other bits to 1 mean "interrupt ocurred"? Of cause I can se, that it means that they can't happen again before they're cleared, is that what the purpose is? else why not set all the bits to 0? |
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Oswald
Registered: Apr 2002
Posts: 5094 |
"storing $7f to dc0d/dd0d clears all bits in the irq mask" |
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
Quote:Yes bit 7 makes sense, but what I don't understand is: isn't setting all the other bits to 1 mean "interrupt ocurred"?
No. Be aware that if you read $DC0D you access a different register than when you write $DC0D.
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oleoleo2
Account closed
Registered: Oct 2008
Posts: 21 |
Graham: That cleared it up a little bit, but I still haven't got an answer to what it actually means to set bit 0-4 to 1, why doesn't $00 clear all irq's too?
Does it mean: "clear the flags on the ones that is set to 1"? because then the bit 0-4 = '1' makes perfectly sense.. |
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Oswald
Registered: Apr 2002
Posts: 5094 |
bit 7 defines what value to write into the rest of the bits. if any of the rest of the bits is set to '1' then value of bit 7 will be written to it.
think of dc0d as an interface. the cia chip will not use directly the value written in here. neither you access the same inner register upon read/write.
$7f -> dc0d will clear all bits.
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oleoleo2
Account closed
Registered: Oct 2008
Posts: 21 |
Thanks Oswald!
It makes sense now.. |
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
If the IRQ mask was designed without set/clear bit, you would have to do something like this to set/clear an IRQ:
LDA $DC0D
ORA #??
STA $DC0D
or
LDA $DC0D
AND #??
STA $DC0D
This has two disadvantages: You need to read the IRQ mask (which is not directly possible on the CIA because reading accesses the flags not the mask) and the setting/clearing is no atomic operation so it's not IRQ save.
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daison
Registered: May 2005
Posts: 90 |
Nice topic, I was wondering about this stuff myself lately. |
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Testa
Account closed
Registered: Oct 2004
Posts: 197 |
yeah me too... very interesting.. |
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oleoleo2
Account closed
Registered: Oct 2008
Posts: 21 |
Quote: If the IRQ mask was designed without set/clear bit, you would have to do something like this to set/clear an IRQ:
LDA $DC0D
ORA #??
STA $DC0D
or
LDA $DC0D
AND #??
STA $DC0D
This has two disadvantages: You need to read the IRQ mask (which is not directly possible on the CIA because reading accesses the flags not the mask) and the setting/clearing is no atomic operation so it's not IRQ save.
Yes but it should be possible anyway with mutual exclusion, and to enable/disable interrupts at the right moments. It would complexify the programs a little bit though. |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: Yes but it should be possible anyway with mutual exclusion, and to enable/disable interrupts at the right moments. It would complexify the programs a little bit though.
Mind you, that it would be possible for IRQs using SEI/CLI ($dcxx), but not for NMIs ($ddxx). |
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
Also there are applications where the added possible IRQ latency is no option. And ofcourse the CIA had to be good enough for those too.
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oleoleo2
Account closed
Registered: Oct 2008
Posts: 21 |
Yeah, but if the IRQ mask was designed in a different way, the processor was probably too, and the applications would have been made to fit the system (I think though this should be in under another topic don't you? :).. |
