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Raistlin
Registered: Mar 2007
Posts: 570 |
100% versions..? Party versions..? etc..?
So, I was wondering ...
Both "Delirious 11" and "X Marks the Spot" have the RESTORE key crash... and "X Marks" has a last minute glitch that crept in...
For myself I'd love to release a 100% version ... but I also kinda wouldn't - because doing so "dirties" the CSDB releases somewhat ... there'd then be something like an "X Marks Party Version" and "X Marks 100% Version" sullying the charts ........
I know Comaland had a 100% version, I can see it right now sat nicely at #2 in the charts ... but that version has more changed since the party version than what I'd likely do...
What do others think? Leave the demos alone and move on .. or go back and fix them. |
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soci
Registered: Sep 2003
Posts: 474 |
Not quite as much. It's 8 to 10. |
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Oswald
Registered: Apr 2002
Posts: 5022 |
"Set CIA2 timer A period to 9 cycles and set CIA2 timer B to count 7 timer A underflows (9 cycles * 7 = 63 cycles), then let timer B trigger interrupts, NMI vector still pointing to timer A counter ($dd04).
Et voilà, one timer NMI per rasterline with only 9 interrupt handlers "
instant erect penis. thats beautiful :) |
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Krill
Registered: Apr 2002
Posts: 2850 |
Quoting sociNot quite as much. It's 8 to 10. Not so rhetorical a question then, eh? :)
Anyways, yes, point taken. So 21 interrupt handlers with the two-timers setup in the worst case. And well, the extra interrupt handlers only reachable by hitting restore would just be an RTI each, anyways.
However... all 8-cycle instructions are undocs, and thus the maximum interrupt delay for "legal" code would be 9 cycles, which fits neatly with the 9-7 scheme. |
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Raistlin
Registered: Mar 2007
Posts: 570 |
Thanks everyone :-)
I'll have a think about this... I've never played much with the CIA timers to be honest... and I've no idea whether that's allowed when using Spindle? I'll see... |
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Krill
Registered: Apr 2002
Posts: 2850 |
Perfectly fine with other loaders that have optional frameworks. :)
Be aware of different CIA revisions vs. different interrupt delay, though. |
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soci
Registered: Sep 2003
Posts: 474 |
Still the 7 cycle modify absolute indexed instructions (like LSR $1000,x) need to be avoided as jump targets. The 9*7 scheme can compensate up to 8 cycles only.
But this special case shouldn't be too difficult to avoid in practice. |
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hedning
Registered: Mar 2009
Posts: 4602 |
Just ignore the restore-thing, Raistlin. It’s no flaw. What I said at X was ”don’t tell Burglar not to press Restore, as that might trigger him to actually press it” ;) If people feel a need to press restore during the demo, let them have the reward they deserve. |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Quoting sociI think I must ask the following rhetoric question:
What's the worst case interrupt latency of the following code sequences in cycles?
1.
clc
bcc *+2
rts
2.
ldx #1
bne *+2
lsr $1000,x
3.
ldx #1
bne *+2
isb ($10,x)
No page boundary crossing. The relevant question is: what range of interupt latency are we dealing with? I.e., how many different states do we have upon entering the irq?
IIRC, when I examined this long ago, I found this (going through the examples above):
for 1. min latency of +1 (irq happens on 1st cycle of "clc"), max latency of +7 (irq occurs on 2nd cycle of bne)
-> 7 different states
for 2. min latency of +1, max latency of +8
-> 8 different states
for 3. min latency of +1, max latency of +9
-> 9 different states
Thus, the 9*7-method presented by Krill should work on any "legal code usage"-occasion. Unless you want to cover the difference between old and new cia by treating it as an additional latency cycle (which would raise the no. of states given above by one in every case).
Correct me if I'm wrong, but I'm rather sure that the behaviour was like this... |
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Krill
Registered: Apr 2002
Posts: 2850 |
If i read Cycles to get into IRQ routine correctly, there are 9 different timer values (8 cycles jitter) for "legal" instructions in the branch-to-same-page case.
11 different values would be the maximum: add one for "illegals" and another one for raster IRQ on line 0, which doesn't apply here. |
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soci
Registered: Sep 2003
Posts: 474 |
I was wrong, sorry.
Copyfault is right, the taken branch is only adding a single cycle and therefore 9 interrupts will covers all cases, including illegal opcodes.
More testing and less talking for me next time ;) |
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