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Papademos
Account closed
Registered: Jan 2011
Posts: 8 |
1541-II Emulation
What does the 6502 receive when reading from unmapped memory? |
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tlr
Registered: Sep 2003
Posts: 1790 |
I would guess that it usually receives what was last on the bus due to the data lines not being driven.
Because there isn't a VIC-II using the bus every other half so it's longer since the bus was driven, maybe there are bit errors in some cases?
Anyone tested this on hw? |
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Krill
Registered: Apr 2002
Posts: 2980 |
Never tested this extensively, but i always saw what was last put on the bus.
That is, the address high-byte, so you see $08 everywhere at $08xx, $09 at $09xx, etc.
A microsecond isn't very long, so i guess bit errors are really rare. |
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Papademos
Account closed
Registered: Jan 2011
Posts: 8 |
Thanks for the quick replies! <3 |
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Trasher
Registered: Sep 2009
Posts: 8 |
Yo! I guess you are talking about truly unmapped areas, not the mirrored parts.. Assuming so, I still would think there could be other effects depending on the state of things.
Example:
A 0300 LDA $1400
Would lead to the address/data bus being:
0300/AD
0301/00
0302/14
1400/Z = 14(?!)
Or would it??? The transition from 0302 to 1400 will take us past other combos which in that case can infact cause other things pushed onto the data bus. It wouldn't normally be latched by the CPU but it could probably interfere with the assumed stored MSB (14).
0302 transitioning to 1400 could pass states:
0302
0000
0400
1400
..and more.. but the obvious problem here is that both 0000 and 0400 will keep the SRAM enabled briefly and possibly get something out of those addresses... Well, it's a late night theory anyway. Never tested it myself on real HW, maybe Krill can kill the theory with practical experience? But your examples of reading 0800/0900 wouldn't have the same issue.
time for zzzzZ.. g'nite |
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Krill
Registered: Apr 2002
Posts: 2980 |
Sorry, no practical experience on that one.
Address transition detection circuits weren't a thing back then, apparently, so yeah, could well be that data from such an intermediate address is put on the bus.
A quick check of the 1541 testsuite that VICE uses didn't bring up any tests for that one, whatever that may mean. =) |
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Trasher
Registered: Sep 2009
Posts: 8 |
I checked the schematics, so for sure there is a chance those intermediate addresses occur. Depends on the timing of the 6502 address bus.
Even if they do, they will be brief, and not sure the SRAM would even react. Also here depends on timing to the decoder... Practical tests would be interesting though. One of these days/years!
If VICE doesn't test it, there might be an opportunity to tell emu-users from real HW-users.. ;) |
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tlr
Registered: Sep 2003
Posts: 1790 |
But if there is no _CS and/or _OE asserted it doesn't really matter if there is a weird address in there briefly. If that is messed up there will be data contention on the bus during normal operation.
Mind you there is a contention issue on at least some of the drive variants, but only when writing the ROM area. That is a logic problem of always issuing a read to the ROM even if it is a write access. |
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Trasher
Registered: Sep 2009
Posts: 8 |
_CS and _OE will be asserted by the decoder, when it sees 0000 and 0400 ... Or in my particular example of going 0302 -> 0000 -> 0400 they would just stay asserted.
Once the address bus reaches the target of 1400 _CS and _OE will be deasserted. 1400 is not mapped at all (even not as a mirror) so the data bus will go Z.
The debate is where the remaining voltage came from. The last stable value seen was 14, but the intermediate addresses 0000 and 0400 are in the SRAM... so if they were there long enough my bet would be the content of 0400 would be on the bus.
I am sure there is contention on that bus all the time, but only briefly so it won't kill any chips.
Offtopic: Funny enough I just compiled your CBM tools, like 20 minutes ago :o I just wish CLD could depack in place and not always use the upper part of memory! /end OT |
