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Forums > CSDb Discussions > EF3 boot/reset VHDL
2020-05-25 11:07
oziphantom

Registered: Oct 2014
Posts: 406
EF3 boot/reset VHDL

I'm playing around with the EF3, but I can't get it to boot in a simulation.

I set the expansion port reset line to 'H' or 'Z' but the EF3 cart still holds it '0' or 'U' depending if I have it in Behavioral simulation or Post-Fit. There are also a lot of 'X' signals.

Does anybody know how it is suppose to boot?
 
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2020-05-28 09:45
oziphantom

Registered: Oct 2014
Posts: 406
Seems =? was added in VHDL 2008 and ISE only goes up to VHDL 200X.

Forcing reset to '1' gives an 'X' while the cart counts, and then restores to what it needs to be. Adding an extra or = 'H' clause, and setting it to 'H'. Makes all the nasty 'X's go away.

So the fix is, init the counter to a valid value explicitly, add an extra check for 'H' in the reset_generator and set the reset_in to 'H' in the test case. Then it basically boots as expected, few 'U's here and there but they look like they are 'don't care' cases.

Thank you for your help.
2020-05-28 11:16
tlr

Registered: Sep 2003
Posts: 1313
Quote: Seems =? was added in VHDL 2008 and ISE only goes up to VHDL 200X.

Forcing reset to '1' gives an 'X' while the cart counts, and then restores to what it needs to be. Adding an extra or = 'H' clause, and setting it to 'H'. Makes all the nasty 'X's go away.

So the fix is, init the counter to a valid value explicitly, add an extra check for 'H' in the reset_generator and set the reset_in to 'H' in the test case. Then it basically boots as expected, few 'U's here and there but they look like they are 'don't care' cases.

Thank you for your help.


Super! Glad to help.

I'm of the opinion that a testbench, at least a very rudimentary one should be supplied with the design. I'm surprised this wasn't the case.
2020-05-28 12:41
oziphantom

Registered: Oct 2014
Posts: 406
he didn't even provide an ise project file and makes it with a custom make file.
2020-05-28 13:35
Groepaz

Registered: Dec 2001
Posts: 9326
if the IDE is anything like quartus, thats more than understandable =)
2020-05-28 15:36
oziphantom

Registered: Oct 2014
Posts: 406
It is very "90s" IDE. However it might be more that it only supports "the paid for" linux distros. You can get the IDE to work on Ubuntu/Debian but the simulator just segfaults instantly (for me).
2020-05-28 15:51
Groepaz

Registered: Dec 2001
Posts: 9326
same with quartus, you need to beat it into shape, copy lots of older binary libs into its directory and fiddle with LD_PRELOAD etc. but i doubt that was the reason, skoe probably just liked makefiles better (and so do i)
2020-05-28 18:33
tlr

Registered: Sep 2003
Posts: 1313
+1 for Makefiles. He probably didn't have a project file himself. And yes, ISE is quite old by now (2013) so it's going to be a pain getting running. Vivado which is the current Xilinx toolset runs ok on Ubuntu 20.04 LTS only needing a few legacy libs apt-getted so that's good.
2020-05-28 19:04
Groepaz

Registered: Dec 2001
Posts: 9326
i use a quite old quartus (13)... and yuck. i avoid the IDE at all cost :)
2020-05-28 20:12
oziphantom

Registered: Oct 2014
Posts: 406
sure but also iSIM ;) I tried GHDL which will compile the ISE libs, but this project wouldn't run in it, didn't try too hard though.

However if I was making a Windows project and I used nmake I would still give an .sln file even if I didn't use it.
2020-05-28 20:17
tlr

Registered: Sep 2003
Posts: 1313
Quote: sure but also iSIM ;) I tried GHDL which will compile the ISE libs, but this project wouldn't run in it, didn't try too hard though.

However if I was making a Windows project and I used nmake I would still give an .sln file even if I didn't use it.


You should be able to simulate in vivado as long as the project doesn't instantiate any device specific entities. The xsim included in vivado is a lot better than isim.
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