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Flavioweb
Registered: Nov 2011
Posts: 463 |
Opcode Execution time != cpu cycles?
As writed at: http://www.atarimax.com/jindroush.atari.org/aopc.html#TIMES
"
Execution Times
Op code execution times are measured in machine cycles, one of which equals two clock cycles. Many instructions require one extra cycle for execution if a page boundary is crossed; ...
"
This mean that using a Cia timer setup to count system cycles and supposing to starting it just after an LDA #$00 instruction and reading it again (the timer value) after instruction execution, since LDA time is 2 machine cycles the timer value can be 4 (or better... to have a timer value of "0" we need to setup it for starting at 4)? |
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Cruzer
Registered: Dec 2001
Posts: 1048 |
lda #$00 is always two cycles, but other vary, e.g. bne - if the branch is not taken it's 2 cycles, if it's taken it's normally 3, but if the address it's jumping to is on another page, an additional cycles is used, resulting in 4 cycles.
See an overview here:
http://www.oxyron.de/html/opcodes02.html
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Flavioweb
Registered: Nov 2011
Posts: 463 |
Quote: lda #$00 is always two cycles, but other vary, e.g. bne - if the branch is not taken it's 2 cycles, if it's taken it's normally 3, but if the address it's jumping to is on another page, an additional cycles is used, resulting in 4 cycles.
See an overview here:
http://www.oxyron.de/html/opcodes02.html
Ok...
But CIA timer goes from 4 to 0 (3 to 0?) or from 2 to 0 (1 to 0?) during execution of LDA #$00 ? |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
The CIA timer will make two steps. It's clocked at the same speed as the CPU (using the same clock signal). The memory bus is clocked at 2mhz though allowing CPU to access memory while the VIC is reading from memory. Sometimes though the VIC needs to slurp data really fast and steals the whole bus, this is called a bad line, where the CPU won't get any time at all for a moment. |
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WVL
Registered: Mar 2002
Posts: 902 |
slurp. I like that.
sluuurrrppP!!
Can we put that in the VIC article? :)
slurp! |
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
Quoting Flavioweb
This mean that using a Cia timer setup to count system cycles and supposing to starting it just after an LDA #$00 instruction and reading it again (the timer value) after instruction execution, since LDA time is 2 machine cycles the timer value can be 4 (or better... to have a timer value of "0" we need to setup it for starting at 4)?
No, on LDA #$00 you always have 2 clock cycles and also the CIA will always count 2. Both, CPU and CIA use the same 1 MHz clock.
It should be noted that the CPU uses both edges (up and down) of the clock to do something, I think that's what they are trying to say. |
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Flavioweb
Registered: Nov 2011
Posts: 463 |
Quote: Quoting Flavioweb
This mean that using a Cia timer setup to count system cycles and supposing to starting it just after an LDA #$00 instruction and reading it again (the timer value) after instruction execution, since LDA time is 2 machine cycles the timer value can be 4 (or better... to have a timer value of "0" we need to setup it for starting at 4)?
No, on LDA #$00 you always have 2 clock cycles and also the CIA will always count 2. Both, CPU and CIA use the same 1 MHz clock.
It should be noted that the CPU uses both edges (up and down) of the clock to do something, I think that's what they are trying to say.
Maybe that 1 "system cycle" are 2 edges, but 1 "clock cycle" is only 1 edge ?
So, if in a pal system with clock at 0,9875MHZ there are 987.500 "edges" per second, the cia can count "only" 493.750 "cycles" per second.
And the cpu to -execute- the LDA #$00 uses 2 -system- cycles that match at 4 "edges" or clock cycles...
correct? |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
Quote:Can we put that in the VIC article? :)
this stuff is explained right at the beginning of said article, *afaik* =)
other than that i recommend - especially for a beginner - to completely ignore the "machine cycle" vs "cpu cycle" thing. its the same in all practical situations anyway :) |
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
Quoting FlaviowebMaybe that 1 "system cycle" are 2 edges, but 1 "clock cycle" is only 1 edge ?
http://en.wikipedia.org/wiki/File:SquareWave.gif
Take a look at that graph: 0.0 to 1.0 is one cycle.
Quote:So, if in a pal system with clock at 0,9875MHZ there are 987.500 "edges" per second, the cia can count "only" 493.750 "cycles" per second.
No, there are 1 million "high" states per second, each of them followed by a "low" state. That's the definition of a "cycle": It repeats on and on.
Quote:And the cpu to -execute- the LDA #$00 uses 2 -system- cycles that match at 4 "edges" or clock cycles...
correct?
It's 2 clock cycles. The rest is pretty much irrelevant on the software side. What groepaz said: On 6502 machine cycles do not matter at all. You can completely ignore that something like that exists.
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Copyfault
Registered: Dec 2001
Posts: 478 |
Quote: Ok...
But CIA timer goes from 4 to 0 (3 to 0?) or from 2 to 0 (1 to 0?) during execution of LDA #$00 ?
Be careful with value '0' in timer regs. In theory, once a CIA timer is started it counts down from its inital value to zero. In reality the timer takes the init value again when reaching the 'zero state'. So it rather looks like this:
initial value e.g. = 4
at next clock cycle = 3
at next clock cycle =2
at next clock cycle = 1
at next clock cycle = 4
(in one shot mode, it stops here; otherwise it continues like this:)
at next clock cycle = 4
at next clock cycle =3
etc.
Confused me a lot when I had my first try with the CIA timers. |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
also that is completely irrelevant unless you are trying to use the timer value right before it wraps. i cant tell any practical situation where this is true right now to be honest :o) |
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