[CSDb] - User Forums - C-64 coding cargo cults

You are not logged in - nap

CSDb User Forums

Forums > C64 Coding > C-64 coding cargo cults

2020-01-14 13:33

Krill

Registered: Apr 2002
Posts: 2980

C-64 coding cargo cults

The most-discussed coding cargo cult on the C-64 is probably SEI/CLI around interrupt setup code.

Here's another one: acknowledging VIC raster interrupts.

According to the datasheet http://archive.6502.org/datasheets/mos_6567_vic_ii_preliminary... an active VIC interrupt is acknowledged by writing a "1" to the corresponding bit in $d019.

The usual way to achieve this seems to be "DEC $D019" and to a lesser extent other read-modify-write instructions, saving a few bytes and/or cycles compared to "LDA $D019 : STA $D019" or "LDA #$xF : STA $D019".
This works because RMW instructions on 6502/6510 read a value (here, the pending interrupts) and write the same value again (clearing the interrupt latches) before writing the modified value.
This is also why this technique does not work on SuperCPU's 65816 in native mode, as its RMW instructions lack the dummy-write of the unmodified value.

Now, the cargo cult bit is this: For raster interrupts, it suffices to write any value with bit 0 set (likewise for other VIC interrupts). Clearing all VIC interrupts can be achieved by writing any value with bits 0..3 set.

So, you can save 2 cycles by simply recycling any register value that happens to have bit 0 set, writing that one to $d019 to acknowledge a VIC raster interrupt.

Please post other coding cargo cults here. =)

... 40 posts hidden. Click here to view all posts....

2020-02-10 06:24

ChristopherJam

Registered: Aug 2004
Posts: 1409

Here's another one.

"You can avoid the ADSR bug by using a specific register write order, independent of instrument design"

Um, just no. You can certainly avoid breaking many well behaved instruments by not deviating from the write order they were designed for, but if you're porting instruments from a routine that used a different ordering there's a fair chance you will break them by switching to your favourite.

The advice given just seems to work because
a) many routines already use the same order.
and
b) writing register 04 after register 05 at start of note avoids changing attack just after setting the gate bit, which can be an issue if the preceding note had a long attack and you don't want to stall a fast one. (A functional HR can also avoid this issue)

The important thing is not using a register write to switch from a slow (high register value) rate to a fast one, unless you desire or can tolerate a 33ms freeze.

It makes no difference whether the rate change comes from switching the value for the current envelope phase (eg changing attack after setting gate), or from toggling the gate bit (eg setting gate to change from decay rate to attack rate).

Previous - 1 | 2 | 3 | 4 | 5 - Next

Refresh

Subscribe to this thread:

You need to be logged in to post in the forum.

Search the forum:
Search for in
All times are CET.

Search CSDb

Advanced

Users Online

A3/AFL
Laurikka
algorithm
Guests online: 95

Top Demos

1 Next Level  (9.7)
2 13:37  (9.7)
3 Mojo  (9.7)
4 Coma Light 13  (9.6)
5 Edge of Disgrace  (9.6)
6 What Is The Matrix 2  (9.6)
7 The Demo Coder  (9.6)
8 Uncensored  (9.6)
9 Comaland 100%  (9.6)
10 Wonderland XIV  (9.6)

Top onefile Demos

1 Layers  (9.6)
2 No Listen  (9.6)
3 Cubic Dream  (9.6)
4 Party Elk 2  (9.6)
5 Copper Booze  (9.6)
6 Rainbow Connection  (9.5)
7 Dawnfall V1.1  (9.5)
8 Onscreen 5k  (9.5)
9 Morph  (9.5)
10 Libertongo  (9.5)

Top Groups

1 Performers  (9.3)
2 Booze Design  (9.3)
3 Oxyron  (9.3)
4 Triad  (9.3)
5 Censor Design  (9.3)

Top Swappers

1 Derbyshire Ram  (10)
2 Jerry  (9.8)
3 Violator  (9.7)
4 Acidchild  (9.7)
5 Cash  (9.6)

Page generated in: 0.035 sec.