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Forums > C64 Coding > useless opcodes riddle - wtf is up with LAS and TAS?
2014-11-07 23:10
chatGPZ

Registered: Dec 2001
Posts: 11523
useless opcodes riddle - wtf is up with LAS and TAS?

Due to my emulator related activities in the last year(s) i digged more into the so called "illegal" opcodes, and the result is a nice (hopefully) PDF that i'll publish soonish (when some of you lazy bastards are done proofreading =D) - which includes complete state of the art reference to all of these, plus a bunch of real world examples on how to use these (sometimes very weird behaving) instructions... (in large part provided by bitbreaker, thumbs up!) Its about time for a comprehensive document on this topic that is suitable for normal people =)

however, two opcodes seem to be completely useless and so far i cant think of what to use them for in real world code:
- LAS abs,y ($BB) (A,X,SP = addr & SP)
- TAS abs,y ($9B) (SP = A & X ; addr = SP & addrhi+1)

if any of you have used these before, or for whatever reason have an idea on what to do with them - let me know please, this is your chance to earn some karma upgrade points :o)

(and as a sidenote, some not so obvious *short* snippets that are using SLO, RLA, RRA or ISC are welcome too)

let's bust some more myths!
 
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2014-11-08 09:57
doynax
Account closed

Registered: Oct 2004
Posts: 212
To my shame I must confess that I haven't found any use for LAS or TAS either.

You'd think TAS would be useful for clearing all of the registers and stack pointer during initialization but LXA #$00/TAY/TXS is a byte shorter, plus you probably want reset S to $FF anyway.

As for SLO/SRE I may have mentioned this before but below is the host side of a two-bit IRQ transfer running in 64 cycles per byte, including loop overhead. A asynchronous IRQ protocol works by toggling ATN, then waiting for the maximum delay period when the drive can be relied on to have the results back before sampling them and toggling ATN for the next bit pair.

By using the SLO/SRE RMW instructions we can both sample DATA/CLK and toggle ATN within two cycles inside the same instruction, instead of four as you would get with separate EOR/STA.
	ldy #%00000100

	;Assert ATN
loop:	arr #%11111010		;cdab00--
	arr #%11111010		;dcdab00-
	ror			;cdcdab00
	sre $dd00-4,y		;cefdaB--

	;Release ATN
	sty $dd00
	alr #%11111100		;0cefdaB0
	sta merge+1
	slo $dd00		;hcef1--0

	;Assert ATN
	and #%10000000		;h0000000
merge:	adc #%00000000		;hcefdaBg
	sta sector,x
	sre $dd00-4,y		;0ab001--

	;Release ATN
	inx
	sty $dd00
	beq break
	and #%01100000		;0ab00000
	slo $dd00		;dab01---
	bne loop		;(BRA)
2014-11-08 11:28
lft

Registered: Jul 2007
Posts: 369
@doynax: Although it makes some assumptions about which vic bank is active, right?
2014-11-08 19:13
Copyfault

Registered: Dec 2001
Posts: 487
Hey Groepaz,

Ninjas 6-Sprites-over-FLI-routine makes heavy use of SLO and RRA (maybe also RLA, not 100% sure), but I guess this example is already covered in the pdf ?!?

I've never used LAE/SHS ($bb/$9b) up to now. As you are looking for "real world examples" I guess that you completely found out what this "unstability" (which is usually connected to both opcodes) really means, right?


Looking forward to reading this paper;)

Bye-

CF
2014-11-08 19:47
chatGPZ

Registered: Dec 2001
Posts: 11523
ninja contributed that routine, yes :) and yes, the instabilities are covered :)
2014-11-08 22:13
doynax
Account closed

Registered: Oct 2004
Posts: 212
Quoting lft
Although it makes some assumptions about which vic bank is active, right?
Yes, only banks 0 and 3 work and IRQ-safe switching eats 10 cycles over $dd02 fiddling.

Plus the 14-cycle response is pushing it, famously failing on the 1571DCR in 1 MHz mode.
2014-11-08 23:01
chatGPZ

Registered: Dec 2001
Posts: 11523
forgot: yes, only "real world" examples are useful, i HAVE used these opcodes in test programs (look in VICE repository)
2014-11-09 17:46
chatGPZ

Registered: Dec 2001
Posts: 11523
who would have though =)
2014-11-09 20:44
Cruzer

Registered: Dec 2001
Posts: 1051
The only thing I have used TAS for is for being impressed by how much stuff the CPU can do in 5 cycles. Too bad it's useless stuff.
2014-11-09 23:35
Martin Piper

Registered: Nov 2007
Posts: 739
Maybe it's time for an optimising assembler that suggests replacement code by scanning for known instruction sequences.
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