| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
Left/Right Border switching in middle of rasterline
The last days i experimented a little with bit 3 of $d016. I had the brainfart to broaden the border on the left and keep it normal on the right. Disappointingly, this seems to work only in every non badline. If i try to switch bit 3 of $d016 during a badline i either get both left and right borders equal or i turn off the border completely for the next rasterline. Does somebody have an explanation in terms of internal VIC timing? I also tried modifying the timing with sprites or HSP to be able to write to $d016 in the correct cycle. |
|
| |
Oswald
Registered: Apr 2002
Posts: 5094 |
r u sure you time it right? sounds like youre either too early or too late. |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
no, i tested every cycle in the applicable range.
if i switch border to broad a rasterline earlier than the badline and then go every cycle through of setting border back to normal, then first left and right border are broad until i add one cycle and then both borders are normal.
Btw: X64 lets me switch during a badline, but X64sc and original hw not. |
| |
lft
Registered: Jul 2007
Posts: 369 |
You'd have to reset to narrow border in cycle 55. (It needs to be wide during the badline DMA, then become narrow before the first half of cycle 56.) But you can't do that, since the write access will happen on cycle 12 instead. |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
Ok, but what is the difference than to the other way round, when one opens the border?
Isn't it the same cycle the write has to be performed? |
| |
lft
Registered: Jul 2007
Posts: 369 |
Nope, then you want the vic to "miss" both occasions where the border might be turned on. So you reconfigure it during cycle 56. In your scenario, you want it to "hit" the first occasion. |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
So in cycle 55 DMA is still going on while in cycle 56 it's already over. That's why cpu can't access $d016 in cycle 55.
Perhaps one should try this with RamEx or SCPU? |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
that doesnt enable you to write to registers when a DMA is going on either :) |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
No, i meant using reu and dma transfer to $d016 |
| |
Oswald
Registered: Apr 2002
Posts: 5094 |
VICII will either read those 40 bytes on a badline or display garbage. guess which will happen with REU attached ?
btw why the fuck do anyone call that DMA ? its a total misuse of the term:
Direct Memory Access (DMA) is a capability provided by some computer bus architectures that allows data to be sent directly from an attached device (such as a disk drive) to the memory on the computer's motherboard. The microprocessor is freed from involvement with the data transfer, thus speeding up overall computer operation. |
| |
Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Maybe you could postpone the badline condition until after the left border edge? Then you may be able to change $d016 in the left border and change it back again after it. Then force a badline condition. This will mess with the graphics on the badlines, I suppose. (If I understand it correctly, this is VSP, isn't it?). |
| |
lft
Registered: Jul 2007
Posts: 369 |
Quoting Oswaldbtw why the fuck do anyone call that DMA ? its a total misuse of the term
It's correct usage of the term. DMA can also be in the direction from memory to peripheral (as in the case with the VIC accessing main memory without CPU involvement). I don't know why the definition you quoted says otherwise. |
| |
lft
Registered: Jul 2007
Posts: 369 |
Quoting Monte CarlosSo in cycle 55 DMA is still going on while in cycle 56 it's already over. That's why cpu can't access $d016 in cycle 55.
Perhaps one should try this with RamEx or SCPU?
No, DMA is going on until (including) cycle 54. But you can't write anything on the first available cycle, because that write is swallowed up during the three write-only cycles (normally 12-14).
All of this is described quite clearly in the vic article. |
| |
lft
Registered: Jul 2007
Posts: 369 |
Quoting Color BarMaybe you could postpone the badline condition until after the left border edge? Then you may be able to change $d016 in the left border and change it back again after it. Then force a badline condition.
Yes, that should work.
Quote:"Color Bar"]This will mess with the graphics on the badlines, I suppose. (If I understand it correctly, this is VSP, isn't it?).
It is VSP if the badline condition was triggered in idle mode. But you could also trigger it from display mode. For instance, you could use the "repeat row" trick to go from RC=7 to RC=0 without having a new badline. Then in the middle of that line, you can force a badline condition, which creates a partial FLI line (with the FLI bug somewhere in the middle of the line). |
| |
Oswald
Registered: Apr 2002
Posts: 5094 |
Quote: Quoting Oswaldbtw why the fuck do anyone call that DMA ? its a total misuse of the term
It's correct usage of the term. DMA can also be in the direction from memory to peripheral (as in the case with the VIC accessing main memory without CPU involvement). I don't know why the definition you quoted says otherwise.
its not correct usage, DMA is a technique to speed up I/O, esp. ment to ease up the CPU from the grunt work of copying bytes. The VICII is nor a peripheral, nor there's anything to speed up. Its wired into the system from day 0. There's no cpu job to speed up. There's no I/O. There's no peripheral.
DMA was invented after the c64 was released. How could it have DMA then ? But if you insist then we should call cpu mem accesses DMA too. Eventho it implies there's a no direct mem access too, which isnt there..
DMA stands for Direct Memory Access, a capability in modern computers that allows peripheral devices to send data to the motherboards memory without intervention from the CPU.
Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels |
| |
Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Quoting lft
All of this is described quite clearly in the vic article.
Yes, but I'm afraid mastering it requires a lot of experimenting. |
| |
lft
Registered: Jul 2007
Posts: 369 |
Quoting Oswaldits not correct usage, DMA is a technique to speed up I/O, esp. ment to ease up the CPU from the grunt work of copying bytes.
The video interface controller is clearly an output device. (Actually, it's doing lightpen input too, but that part doesn't benefit from DMA.)
The fact that VIC reads memory directly does offer a performance advantage over solutions that involve the CPU, such as the VDC in the C128.
Quoting OswaldThe VICII is nor a peripheral
Neither is the VDC. But the VIC uses DMA and the VDC doesn't. Also, peripherals on the cartridge port have access to DMA using the exact same lines that VIC uses, and for the exact same purpose, with one exception: The peripherals also need to stay out of the way when the VIC needs the bus, because the VIC has highest DMA priority.
Quoting OswaldIts wired into the system from day 0. There's no cpu job to speed up.
There's no CPU job to speed up precisely because the VIC has direct access to the memory.
Quoting OswaldDMA was invented after the c64 was released.
That's incorrect. I don't know exactly when it was invented, but in this patent from 1978 for a shared DMA controller, we can read:
The concept of direct memory access is well known in the art. Generally speaking, this concept allows a central processing unit to load a subsystem device controller with the instructions and data necessary to initiate and carry out a data transfer between the memory and the peripheral device connected to and controlled by the subsystem device controller.
Quoting OswaldBut if you insist then we should call cpu mem accesses DMA too.
No, because the CPU would be involved during such accesses. |
| |
oziphantom
Registered: Oct 2014
Posts: 490 |
VSP puts you into 39x25 mode. |
| |
oziphantom
Registered: Oct 2014
Posts: 490 |
DMA is where something gets data from memory with out it being moved by the CPU. So the VIC grabs the data it wants we don't have to load the data into one of its registers for it to display data. Like you do on the 2600. The 128s VDC also has DMA but it gets the data from its VRAM. The VDC has a programmable DMA engine in that you can get the VDC to DMA copy data from one part of its VRAM to another. The VIC has fixed DMA.
The SID does not have DMA and to change music we must use the CPU to change the SID's registers. Paula has DMA so when she needs more sample data she will take over the bus and get her data from RAM. So the VIC,VDC DMA, the CIAs,SID don't DMA. |
| |
Flavioweb
Registered: Nov 2011
Posts: 463 |
I can't understand one thing:
how is possible to have left border opened and right closed?
If you open border at cycle 56, it "still open" since cycle 17 of next line.
If you set "CSEL=0 to CSEL=1 in cycle 17" border still open since next line cycle 17 (From Vic Aritcle: "Likewise the
horizontal border can be prevented from turning off by switching from CSEL=0 to CSEL=1 in cycle 17")...
Or i'm missing something? |
| |
tlr
Registered: Sep 2003
Posts: 1790 |
Quote: I can't understand one thing:
how is possible to have left border opened and right closed?
If you open border at cycle 56, it "still open" since cycle 17 of next line.
If you set "CSEL=0 to CSEL=1 in cycle 17" border still open since next line cycle 17 (From Vic Aritcle: "Likewise the
horizontal border can be prevented from turning off by switching from CSEL=0 to CSEL=1 in cycle 17")...
Or i'm missing something?
It isn't possible. The OP was about having a one char wider border on left side but normal width on the right. |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
In first place this question was about making the border broad at the left and small at the right. It's just when experimenting with adding and leaving cycles you occasionally end up in opening the border, instead.
About the VSP:
I tried to VSP in line $30 to delay all the internal vic timing for the whole screen. However this did not solve the puzzle because still i was not able to broaden the left border and make normal the right border.
Do you mean i should try VSP on the same line i want the border switched? |
| |
soci
Registered: Sep 2003
Posts: 480 |
Just use a border coloured sprite on the left side for the same effect. |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
Quote: its not correct usage, DMA is a technique to speed up I/O, esp. ment to ease up the CPU from the grunt work of copying bytes. The VICII is nor a peripheral, nor there's anything to speed up. Its wired into the system from day 0. There's no cpu job to speed up. There's no I/O. There's no peripheral.
DMA was invented after the c64 was released. How could it have DMA then ? But if you insist then we should call cpu mem accesses DMA too. Eventho it implies there's a no direct mem access too, which isnt there..
DMA stands for Direct Memory Access, a capability in modern computers that allows peripheral devices to send data to the motherboards memory without intervention from the CPU.
Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels
WHAT THE ACTUAL FUCK.
whatever the source for this "knowledge" is - delete it from your memory. srsly. |
| |
lft
Registered: Jul 2007
Posts: 369 |
Quoting Monte CarlosAbout the VSP:
I tried to VSP in line $30 to delay all the internal vic timing for the whole screen.
There is no way to delay all the internal vic timing for the whole screen. VSP is for increasing the video matrix offset by 1..39. |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
Ok, maybe not for the whole screen but the badline starts as soon as the badline condition is fulfilled. So the appropriate write to $d011 should start the badline condition anywhere in the visible area and this also starts the internal VIC timing of the rasterline. Or did i understand something wrong, here? |
| |
Martin Piper
Registered: Nov 2007
Posts: 722 |
Writing to the VIC registers basically instructs it to directly read certain memory into its own internal state for later processing/display. Hence the VIC does DMA. |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
Maybe we should start a new topic about whats DMA and whats not if there is so much interest. |
| |
Peiselulli
Registered: Oct 2006
Posts: 81 |
Write demos for the Atari 2600. THAT is a computer without DMA ... |
| |
Oswald
Registered: Apr 2002
Posts: 5094 |
Quote: Writing to the VIC registers basically instructs it to directly read certain memory into its own internal state for later processing/display. Hence the VIC does DMA.
VICII reads the memory wether the cpu touches any of its registers or not. its a wired behaviour. if you skew your perspective enough tho I admit it can be viewed as DMA, but thats not my view.
DMA usually refers to speed up copying between memory and a true I/O device, or memcopy, etc. usually involves a DMA controller too. |
| |
JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: VICII reads the memory wether the cpu touches any of its registers or not. its a wired behaviour. if you skew your perspective enough tho I admit it can be viewed as DMA, but thats not my view.
DMA usually refers to speed up copying between memory and a true I/O device, or memcopy, etc. usually involves a DMA controller too.
So writing to $d011 doesn't affect that "hardwired" behaviour at all? :) |
| |
Oswald
Registered: Apr 2002
Posts: 5094 |
Quote: So writing to $d011 doesn't affect that "hardwired" behaviour at all? :)
almost any register change affects it :) but yeah the way it stops the cpu to access mem via bus lines resembles certain modern DMA behaviour. |
| |
lft
Registered: Jul 2007
Posts: 369 |
Quoting Monte CarlosOk, maybe not for the whole screen but the badline starts as soon as the badline condition is fulfilled. So the appropriate write to $d011 should start the badline condition anywhere in the visible area and this also starts the internal VIC timing of the rasterline. Or did i understand something wrong, here?
True, but you only change where the badline starts. It always ends at a fixed position (leaving you at cycle 55). |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
Quote:DMA usually refers to speed up copying between memory and a true I/O device, or memcopy, etc. usually involves a DMA controller too.
DMA usually refers to "direct memory access" - which is when anything that isn't the main CPU accesses the memory (without CPU intervention). no more no less. |
| |
Frantic
Registered: Mar 2003
Posts: 1648 |
EDIT: Nothing (but I certainly agree wth Gpz, Lft and others) |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
I now tried the line doubling trick. By decreasing $d011 by one on the right side of the line before the natural badline, the timing can be adjusted so that the left border is broad and the right is small (at least in x64sc). This applies to the first rasterline of the charrow duplicate. However, in the duplicated charrow an idle byte appears in column 39.
However, this could be fixed by using a modified charset with the last char having the desired pattern. |
| |
tlr
Registered: Sep 2003
Posts: 1790 |
Quote: I now tried the line doubling trick. By decreasing $d011 by one on the right side of the line before the natural badline, the timing can be adjusted so that the left border is broad and the right is small (at least in x64sc). This applies to the first rasterline of the charrow duplicate. However, in the duplicated charrow an idle byte appears in column 39.
However, this could be fixed by using a modified charset with the last char having the desired pattern.
Although I believe we got x64sc mostly right, make sure to verify that on a real c64 first. |
| |
Mixer
Registered: Apr 2008
Posts: 452 |
Picture or screen capture would be worth a thousand words. |
| |
Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
I guess you could also make the left border small and the right border broad instead. Do you also see an idle byte then? |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
The idle byte seems to be independent of how the border is displayed. Of course i test it on the real thing, however i transferred last time before i made my initial post.
At this time x64sc and my 128D in 64 mode showed same output.
Sorry, the code is on my 13" notebook already packed to use the noon break on work for coding..
I can upload a screenshot tomorrow. |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
Ok, this works. Just follow the link
https://www.dropbox.com/s/4itioa1abhl6oc3/leftBroadRightSmall.P..
Meanwhile i tested it on original. It works and it has the same output as x64sc. You got it right. |
| |
Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Cool. The idle byte seems to be shifted down by 1 line. Where does it get its color from?
Can't you hide it by making the right border broad instead? |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
From the lo nibble of the opcode following the st? $d011 (?=a|x|y). |
| |
Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Quoting Color BarCan't you hide it by making the right border broad instead?
I guess that's not very handy for a text scroller. |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
Not even in arabic language, because a major bug would appear on the left side independent on scroll direction. |
| |
Digger
Registered: Mar 2005
Posts: 437 |
Looks like you've done the impossible MonteCarlos! changed the color in the middle of the char second row at the very right ;-D)
I guess one could use bitmap mode without badlines to create 39 column wide scroll using VSP? |
| |
Monte Carlos
Registered: Jun 2004
Posts: 359 |
Where do you see a split in the middle of a char?
Did you use VICE or real machine?
I'm not aware of that what you want to tell me at the moment. |
| |
Digger
Registered: Mar 2005
Posts: 437 |
@MC: Haha, in your screenshot! Second row, the very last char. I am not sure what's going on there but it looks like you've split the atom ;-) |
| |
ChristopherJam
Registered: Aug 2004
Posts: 1409 |
That's a blue $ff character! The split is between char foreground and $d021 |
| |
Oswald
Registered: Apr 2002
Posts: 5094 |
the latest shape demo uses sprites to achieve a 41 char wide screen for 40 column scroll. |
| |
Digger
Registered: Mar 2005
Posts: 437 |
Right Oswald well spotted!
@CJ: Ah, haha how could I miss that?! |
| |
Compyx
Registered: Jan 2005
Posts: 631 |
isn't that like a normal scroll with sprites to solve the colum -1 thing? Ie. not really splitting anything? |
| |
Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
I noticed that if you change from hires to character screen during a line, that the graphics change 16 pixels / 2 chars later than the colors (for 8565 at least, for 6569 the colors change 2 pixels earlier). In other words, you can see 2 hires characters with the colors of a normal text screen (and vice versa when you change back). I guess if you switch 1 character into the left border, and fill the leftmost column of the hires screen, you can also fake a wider left border. The badlines are again a problem, though, and soft scrolling would be difficult. When the lower 3 bits of $d016 are changed, the position where color changes doesn't move, only the graphics shift. |
