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TWW
Registered: Jul 2009
Posts: 545 |
$dc0d madness
how come a lot of people set up their raster IRQ's like:
lda #$01
sta $d01a
lda #$7f (?)
sta $dc0d
and not just simply:
ldx #$00 // I believe 0 = mask and 1 = don't mask but it isn't specified in the prog.ref.manual...
stx $dc0d // Mask out all CIA#1 IRQ's
inx
stx $d01a // Mask out all VICII IRQ's minus raster compare
Where does this "#$7f" come from?
or have i missed some kind of importaint point here? |
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Mr. SID
Registered: Jan 2003
Posts: 424 |
AFAIK it works like this:
Bit 7 specifies if you want to clear or set the mask bits. If it's 0 it means clear. A mask bit is only affected by the clear operation, if the corresponding bit in dx0d is set to 1.
So e.g. this would only mask the Timer B IRQ, leaving the other mask bits unaffected:
lda #$02
sta $dc0d
And this would unmask Timer B again:
lda #$82
sta $dc0d
So #$7f masks all CIA IRQs. Makes sense? Or maybe I'm wrong too?
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
Because the register works quite different than you think.
Bit 7 of the register tells if the selected IRQ masking bits get cleared or set. You select an IRQ masking bit by having it's bit set. So if you write $03, the timer A and B IRQ masks will be cleared, but if you write $83 the masks will be set. This way you can modify single IRQ masks without touching the others.
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TWW
Registered: Jul 2009
Posts: 545 |
Alrigth then so a setting of a bitmask:
lda #$83
sta $dc0d
would ENABLE Timer A+B IRQ's from CIA#1
and consequently:
lda #$03
sta $dc0d
would DISABLE Timer A+B IRQ's from CIA#1.
Without touching the state of the other available IRQ's.
does it work in the same way for the VICII IRQ mask register aswell (only inverted use of bit #7)?
lda #$01
sta $d01a // Enable raster comp. IRQ
vs.
lda #$81
sta $d01a // Disable raster comp. IRQ? |
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Mr. SID
Registered: Jan 2003
Posts: 424 |
No, the VIC has just one bit per IRQ source, if you don't want to affect the other ones, you have to mask out the bits yourself. |
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Ninja
Registered: Jan 2002
Posts: 411 |
In almost any case you want to do a LDA $DC0D after clearing all the other CIA interrupts. Bonus point if you find out why by yourself (stuff like AAY64 might help you)... |
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chatGPZ
Registered: Dec 2001
Posts: 11386 |
another bonus point for finding the flaw in
lda $dc0d
sta $dc0d
:)
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Oswald
Registered: Apr 2002
Posts: 5094 |
madness?!
t h i s i s SPARTAAAAAAAAAAAAAA!!!!!!!!!!!!!!!!!!11111 |
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TWW
Registered: Jul 2009
Posts: 545 |
Quote: In almost any case you want to do a LDA $DC0D after clearing all the other CIA interrupts. Bonus point if you find out why by yourself (stuff like AAY64 might help you)...
No fucking clue there was something like AAY64 around (now I know though) but before consulting documentation of such biblical proporsions I am going out on a limb to achieve my bonus point and guess that a LDA $dc0d would ack any outstanding CIA interrupts to avoid accendental triggering of latent CIA IRQ's.
Fucking hell that's one huge sentence eh?
@ Groepaz:
Uncertain what happens when you read bit #7 of $dc0d (@ work and no time to consult AAY64 or test it) but depending of the state of bit #7 you would then disable/enable any occured IRQ. But I'm sure it doesen't work this way anyway... If I got it half right does I gets its another bonus points?
@ Oswald:
freak! |
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Ninja
Registered: Jan 2002
Posts: 411 |
Quoting TWWFucking hell that's one huge sentence eh?
Still you got the point :D
This can be a reason why some demo-parts crash on start "randomly". Forbid interrupts, clear some memory (during that time, a CIA-IRQ may appear and is waiting for interrupts to be allowed again), set up your VIC-IRQ which just clears $d019, allow interrupts - voila, CIA will trigger IRQs endlessly. |
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TWW
Registered: Jul 2009
Posts: 545 |
What I find interesting is that SEI itself only inhibit activation of IRQs but don't stop them from setting bits high in $d019/$dc0d even during a sei-cli. An importaint fact to say the least.
On top of this special care regarding NMI which is totally unaffected by the sei-cli statement must be taken.
@ groepas:
After thinking about it I will say the following about your lda/sta $dc0d.
lda $dc0d // loads status of CIA#1 IRQs / Ack's any IRQs
if A & #%10000000 = 80 (some IRQ occured) then whichever IRQ occured will be masked after sta $dc0d.
if A & #%10000000 = 00 (no IRQ occured) then you would write #00 into $dc0d which means unmask no IRQs. which doesen't make any sense?!
So to summarise: If any CIA#1 IRQ(s) occurs, disable it/them. If no IRQ occurs pretend to be 'leet and shout loudly "I kill LAMERS for free!". (aka. nothing happens^^)
I want my bonus point. This gives me totally 2 points (I assume I got ninja's bonuspoint) and then I donate 1/2 a point to Oswald for his SPPPAAAARTTTAAAA comment. A considerable contribution to this discussion afterall :) |
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Stone
Registered: Oct 2006
Posts: 172 |
No points for you! Come back, one year! |
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TWW
Registered: Jul 2009
Posts: 545 |
I also came to think about the IRQ being pulled low by an event. How long does it take before another IRQ is triggered (coz as I understand it it is the low state not the state change which triggers the IRQ(unlike NMI which relies on state change))?
Stein wtf? |
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Stone
Registered: Oct 2006
Posts: 172 |
Bit 7 being set on write wont disable the IRQs, it will enable them (but they're already enabled, so it's a no-op). In the case where bit 7 is 0, no CIA1 IRQs are enabled, so this is also a no-op. |
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TWW
Registered: Jul 2009
Posts: 545 |
Quote: Bit 7 being set on write wont disable the IRQs, it will enable them (but they're already enabled, so it's a no-op). In the case where bit 7 is 0, no CIA1 IRQs are enabled, so this is also a no-op.
Stolen from AAY64:
$DC0D/56333/CIA1+13: Interrupt (IRQ) Control Register
+-------+------------------------------------------------------+
| Bit 7 | On Read: 1 = Interrupt occured |
| | On Write: 1 = Set Int.-Flags, 0 = Clear Int-.Flags |
| Bit 4 | FLAG1 IRQ (Cassette Read / Serial Bus SRQ Input) |
| Bit 3 | Serial Port Interrupt ($DC0C full/empty) |
| Bit 2 | Time-of-Day Clock Alarm Interrupt |
| Bit 1 | Timer B Interrupt (Tape, Serial Port) |
| Bit 0 | Timer A Interrupt (Kernal-IRQ, Tape) |
+-------+------------------------------------------------------+
On Write: 1 = Set Int.-Flags!
stolen from c64prg:
DC0D 56333 CIA Interrupt Control Register
(Read IRQs/Write Mask)
7 IRQ Flag (1 = IRQ Occurred) / Set-
Clear Flag
4 FLAG1 IRQ (Cassette Read / Serial Bus
SRQ Input)
3 Serial Port Interrupt
2 Time-of-Day Clock Alarm Interrupt
1 Timer B Interrupt
0 Timer A Interrupt
in the bible it says WRITE MASK where Set (1) will clear the flag in contradiction to the AAY64 where it sais 1 = set the flag.
So I got it half right due to shady intel...
This means Oswalds half point is withdrawn.
ps. the masking is the oposite then on the VIC where it is called the mask register and a set bit indicates mask... |
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Stone
Registered: Oct 2006
Posts: 172 |
My reply was a bit clumsily put. What I meant was, when bit 7 is 0, writing back any remaining 1-bits will do nothing, since their corresponding IRQ is already disabled. And yes, you got it half right. |
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Frantic
Registered: Mar 2003
Posts: 1648 |
[edit] |
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TWW
Registered: Jul 2009
Posts: 545 |
Quote: My reply was a bit clumsily put. What I meant was, when bit 7 is 0, writing back any remaining 1-bits will do nothing, since their corresponding IRQ is already disabled. And yes, you got it half right.
The only way bit #7 is clear when you read $dc0d is if there are no IRQ's (The whole point of reading $dc0d is to determine which IRQ got activated besides ack any pending irqs(as I understand it)). so in your example above above would simply be the same as:
lda $dc0d (which with no triggered irqs equals #0(aka lda #0))
sta $dc0d
which would totally do nothing but mess up A and waste some cycles (hence a fail).
if some IRQs got triggered bit #7 would be set and whatever bit 6-0 would be set.
Writing this back would set any corresponding flags high (and in contradiction to $d01a which masks them it will here allow them to occur). Given the fact that they already occured (meaning they where already allowed) it makes no point to allow them more then they already are. also a fail. :)
conclusion: a lda/sta $dc0d does absolutely nothing but ack CIA IRQs, waste cycles and destroy A.
Stick a fork in me I'm done.
However I am still curious about the time it takes for another IRQ to occur if the IRQ event remains unack'ed? |
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Stone
Registered: Oct 2006
Posts: 172 |
Consider yourself stuck |
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Stone
Registered: Oct 2006
Posts: 172 |
EDIT:Quoting Stein What I meant was, when bit 7 is 0, writing back any remaining 1-bits will do nothing But ofcourse, there are no remaining 1-bits. Man, it's been too long... |
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TNT
Account closed
Registered: Oct 2004
Posts: 189 |
Quoting TWWWhat I find interesting is that SEI itself only inhibit activation of IRQs but don't stop them from setting bits high in $d019/$dc0d even during a sei-cli.
SEI affects CPU only, your interrupt sources are two CIAs and VIC-II. 6510 doesn't generate any interrupts (except BRK which doesn't care about SEI) by itself, it just reacts to an external signal. |
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TWW
Registered: Jul 2009
Posts: 545 |
Quote: Quoting TWWWhat I find interesting is that SEI itself only inhibit activation of IRQs but don't stop them from setting bits high in $d019/$dc0d even during a sei-cli.
SEI affects CPU only, your interrupt sources are two CIAs and VIC-II. 6510 doesn't generate any interrupts (except BRK which doesn't care about SEI) by itself, it just reacts to an external signal.
Thank you. This confirms my thoughts further. |
