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TWW
Registered: Jul 2009
Posts: 545 |
Regarding Interrupts
I have some hypothetical questions regarding IRQ interrupts;
#1: If an IRQ event is pulsed (IRQ line pulled low) for a duration of 3-4 cycles and this happens during a 6-7 cycle instruction, can the IRQ be missed by the MPU?
#2: Are the IRQ-flags handled by the MPU or the chips in question (CIA#1/VICII) (I suspect the VIC/CIA)?
#3: If the answer to #1 is yes & #2 is CIA/VIC, would a "missed IRQ" still be flagged?
#4: If an IRQ remains unacknowledged will the latent IRQ event retrigger a interrupt on the CPU after an RTI?
#4.5 I have tested #4 and found it to re-trigger after 6 cycles. Can someone confirm and why 6 cycles?
#5: The interrupt initialization takes 7 cycles wheras the 2 first cycles are described as "internal functions" in a 6502 diagram I saw. What exactly is going on during these 2 clock cycles?
#6: If you ack CIA#1 with a LDA $dc0d, this operation takes 4 cycles. In whihc cycle does the flag(s) actually clear?
#7: Same as #6 just with LDA #$ff, STA $d019.
If there is some documentation around this I would be gratefull for some pointers. And yes I know some of these things could probably be tested and figgured out but hey what's a forum for^^ |
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TWW
Registered: Jul 2009
Posts: 545 |
Note to my self: I'm an idiot!
cheers I got it now thanx fellas. This is what a forum is all about! |
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iAN CooG
Registered: May 2002
Posts: 3194 |
Quote: Note to my self: I'm an idiot!
cheers I got it now thanx fellas. This is what a forum is all about!
Yeah, this is what this forum is about: letting someone to understand and admit he's an idiot!!11
;D |
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tlr
Registered: Sep 2003
Posts: 1790 |
Back to the original issue:
I've done a slightly different test program...
http://vice-emu.svn.sourceforge.net/viewvc/vice-emu/testprogs/i..
It tests what happens if the IRQ is ACKed in cycle 2 of an LDA #<imm>, in cycle 3 of an ORA <abs> and cycle 2 of an LDY <abs>.
The results are indeed interesting. |
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Frantic
Registered: Mar 2003
Posts: 1648 |
@TLR: Would you mind summarizing what you found, in case it does not require an extremely complex explanation? :) I executed that program but since it was not obvious what the chars on the screen meant I didn't bother further. |
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Devia
Registered: Oct 2004
Posts: 401 |
maybe he didn't quite understand the numbers himself, thus the result was interresting ;-)
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Frantic
Registered: Mar 2003
Posts: 1648 |
Well, I didn't necessarily mean to ask for a deeper explanation of *why* the computer/CPU behaves like it does, but rather an explanation of *what* the program says that the computer does. I hope TLR at least knows what his program is doing. :)
For example, in VICE (dunno if VICE is even relevant here) the output looks like this:
CIA-INT / TLR
DC0C: A9 XX 60
--BBBb------------------
AACC---IIIKK------------
DC0B: 0D A9 XX 60
--BBBBb-----------------
AAEEEE--KKKKMM----------
DC0C: AC XX A9 09 28 60
--BBBb------------------
AAEEE--HHMMMMMOO--------
Anyone? :) I understand that the hex numbers are various opcodes, but.. then what? :) |
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assiduous
Account closed
Registered: Jun 2007
Posts: 343 |
the output from Vice looks wrong,the output from the old CIA 6526 looks like this:
CIA-INT / TLR
DC0C: A9 XX 60
--BBBb------------------
AACC--IIIIKK------------
DC0B: 0D A9 XX 60
--BBBBb-----------------
AAEEEE-KKKKKMM----------
DC0C: AC XX A9 09 28 60
--BBBb------------------
AA----HHHMMMMMOO-------- (if there`s no timer B hardware fault)
or like this:
CIA-INT / TLR
DC0C: A9 XX 60
--BBBb------------------
AACC---IIIKK------------
DC0B: 0D A9 XX 60
--BBBBb-----------------
AAEEEE--KKKKMM----------
DC0C: AC XX A9 09 28 60
--BBBb------------------
AA-----HHMMMMMOO-------- (with the timer B hardware fault in some chips)
Hoxs prints correct values for any selected setup. |
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tlr
Registered: Sep 2003
Posts: 1790 |
Quote: Well, I didn't necessarily mean to ask for a deeper explanation of *why* the computer/CPU behaves like it does, but rather an explanation of *what* the program says that the computer does. I hope TLR at least knows what his program is doing. :)
For example, in VICE (dunno if VICE is even relevant here) the output looks like this:
CIA-INT / TLR
DC0C: A9 XX 60
--BBBb------------------
AACC---IIIKK------------
DC0B: 0D A9 XX 60
--BBBBb-----------------
AAEEEE--KKKKMM----------
DC0C: AC XX A9 09 28 60
--BBBb------------------
AAEEE--HHMMMMMOO--------
Anyone? :) I understand that the hex numbers are various opcodes, but.. then what? :)
It works like this:
- start timer
- jsr $dc0b or $dc0c depending on test.
- show contents of $dc0d at the time of ack and if an IRQ occured.
The test is done for timer values of 0-23 (timer B used).
The top line of each test shows the contents of $dc0d.
(B=$82, b=$02, -=$00)
The bottom line shows the number of cycles since starting the test until an IRQ occured. (- means no IRQ)
Test 1: Ack in second cycle of 2 cycle imm instr.
DC0C A9 XX LDA #$xx
DC0E 60 RTS
Test 2: Ack in third cycle of 4 cycle abs instr.
DC0B 0D A9 XX ORA $xxA9 <-- memory prefilled to do ORA #$xx (mostly)
DC0E 60 RTS
Test 3: Ack in second cycle of 4 cycle instr.
DC0C AC XX A9 LDY $A9xx <-- memory prefilled to do LDY #$xx
DC0F 08 PHP <-- this can also be ORA #$28 if the timer hasn't expired yet.
DC10 28 PLP
DC11 60 RTS
No "EEE" in the last test seems to signify that there is a location where the interrupt never occurs.
Hoxs64 indeed does this 100% correctly. Nicely done!
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Graham
Account closed
Registered: Dec 2002
Posts: 990 |
Should be mentioned that there are 2 different CIAs and Hoxs emulates a different one than Vice.
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Rubi
Account closed
Registered: Apr 2002
Posts: 48 |
Quote: Should be mentioned that there are 2 different CIAs and Hoxs emulates a different one than Vice.
But both emulators can switch between 6526 and 6526A in their latest versions (x64sc in VICE). |
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