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2014-01-19 13:15

Flavioweb

Registered: Nov 2011
Posts: 463

Raster, 8 cycles, CIA and other stories...

I write this post trying to clarify what i understand about "stabilizing raster using CIA inverted timer" technique.

From what i read in many post, the first plea of misunderstanding is the "number of delay cycles" from when IRQ is requested to when CPU fires the IRQ code.
Without using illegal opcodes, the "execution time" of opcodes goes from a minumun of 2 to max 7 cycles.
In agreement on this:
http://visual6502.org/wiki/index.php?title=6502_Timing_of_Inter..
the "doIRQ" flag isn't set during LAST opcode cycle.
This mean that we need at least 2 cycles before "end of opcode cycles" to execute the irq.
If IRQ is requested on last cycle of opcode, then also next opcode will be fetched and executed.
But...
What happen with conditional branch opcodes?
BNE, BEQ, and "family" uses 2 cycles if branch isn't taken, and 3 if it is: so... what is last cycle of this opcode?
"Last" cycle is always the second one, and this mead that the "doIrq" is checked only during first cycle.
If the IRQ is requested on 2nd cycle... simply will be fired durnig NEXT opcode... adding 1 cycle to the "jitter".
So, if we have:

LOOP
    ADC ($FF,X)
    INX
    BNE LOOP

and an IRQ is requested on last cycle (2nd) of taken BNE we have 2 cycles from branch + 6 cycles from ADC = 8 cycles jitter.

But there is another thing to consider when setting up a CIA timer that need to be in SYNC with RASTER BEAM: that it needs to be in sync with raster and... not with jitter!
Obvious?
I think large part of the misunderstanding comes from this.
If we set a CIA countdown value of 7, to have 8 values (7...0 (7, 6, 5, 4, 3, 2, 1, 1 exactly)) that is in perfect sync with rasterline 1, when rasterbeam reach cycle 0 of rasterline 2, the CIA timer is delayed by one cycle on PAL machines.
1 line = 63 cycle,
8x8 Cia loops = 64 cycles
so in the first cycle of second line we have a countdown value of "1", but theoretically we must have a value of "8" (minimum possible delay/jitter).

So, best practice, is to set the number of cycles per line as countdown value.

In pratice, we need to consider also a "1 cycle" difference in "time-to-setup-timer" that some CIA model have, related to other models...

But ... roughly, is this.

2014-01-19 15:08

tlr

Registered: Sep 2003
Posts: 1790

The 1 cycle difference between new/old cia is only in the latency for an interrupt to occur. If the cia isn't used to trigger the interrupt you don't need to consider it.

I seem to remember that the timer B underrun behaves differently with regards to the read timer values but can't really find the reference now.

2014-01-19 18:44

Flavioweb

Registered: Nov 2011
Posts: 463

Quoting tlr

The 1 cycle difference between new/old cia is only in the latency for an interrupt to occur. If the cia isn't used to trigger the interrupt you don't need to consider it.

I seem to remember that the timer B underrun behaves differently with regards to the read timer values but can't really find the reference now.

I found this:
http://www.antimon.org/dl/c64/code/stable.txt

If your guess is right, the color will always be changed in the same screen position (neglecting the 7-cycle jitter).  When adjusting the timer, remember that the timers on the 6522 VIA require 2 cycles for re-loading, and the ones on the 6526 CIA need one extra cycle.
Keep trying different timer values until you the screen color changes at one fixed position.

I understand that 6522 need 2 cycles and 6526 need 3 cycles to restart timer...
(Btw, in pratice, i never noticed differences)

2014-01-19 21:30

Cruzer

Registered: Dec 2001
Posts: 1048

As far as I remember, the branch will only add one cycle to the jitter, so in your case when you branch to adc ($ff),y the jitter will go from 6 to 7 cycles. Not sure what happens when the branch crosses a page and therefore takes two extra cycles though.

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