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Forums > C64 Coding > 6502 instruction decoding
2012-02-29 18:14
JackAsser

Registered: Jun 2002
Posts: 2014
6502 instruction decoding

Why is it that STA-opcodes always gets an implicit page-crossing penalty in comparison to their LDA counter parts?

F.e.
lda abs,x is 4/5 depending on page crossing
sta abs,x is always 5 independent of page crossing
 
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2012-02-29 21:07
JackAsser

Registered: Jun 2002
Posts: 2014
RMW has two write cycles? Wow. So, on Nintendo, with auto incrementing vram-pointer when writing to $2007, this would mean that it would increment the pointer TWO times if I do say, INC $2007. Or rather, THREE times because of the one load cycle as well?
2012-02-29 21:11
TWW

Registered: Jul 2009
Posts: 545
Quote: It should be mentioned that STA $1234,X reads from the same address as LDA $1234,X in step 4.

And yes, this wrong read can acknowledge IRQs. Example:

    LDX #$FF
    LDA $DC0E,X

This would read from $DC0D in cycle 4 and $DD0D in cycle 5, acknowledging both, IRQs and NMIs :)


That is amazing! 8-D

so no more:

    lda $dc0d
    lda $dd0d


just:

    ldx #$ff
    lda $dc0e,X


cool!
2012-02-29 21:33
MagerValp

Registered: Dec 2001
Posts: 1078
Quoting Graham
A clean way to acknowledge VIC2 IRQs would be LDA $D019 STA $D019.

Or rather LDA #$FF : STA $d019.
2012-02-29 21:56
iAN CooG

Registered: May 2002
Posts: 3194
I find asl $d019 way simpler, all bits get read/written.
2012-03-01 00:33
JackAsser

Registered: Jun 2002
Posts: 2014
Quote: I find asl $d019 way simpler, all bits get read/written.

Checking out visual6502.org and the forums there it became clear that the actual instruction decoding is just an internal PLA in the CPU. It takes the current opcode and cycle into an array and get an operation value out which it executes.

I want a dump of this ROM. There is one online but it's obviously totally flawed, and the dude who did it also said he didn't know what lines that were what.

Using the visual6502 one can transcribe it properly, but it's a pain to do it. Anybody did it already?
2012-03-01 08:28
MagerValp

Registered: Dec 2001
Posts: 1078
Quoting JackAsser
Using the visual6502 one can transcribe it properly, but it's a pain to do it. Anybody did it already?

No me, but I'm also interested in it. It'd make a pretty awesome cycle exact 6502 emulation core.
2012-03-01 08:33
JackAsser

Registered: Jun 2002
Posts: 2014
Quote: Quoting JackAsser
Using the visual6502 one can transcribe it properly, but it's a pain to do it. Anybody did it already?

No me, but I'm also interested in it. It'd make a pretty awesome cycle exact 6502 emulation core.


Exactly + less code to implement it probably given you implement the ~130 sub operation (compared to 256 special case instruction as we do today more or less)
2012-03-02 18:11
Zer0-X
Account closed

Registered: Aug 2008
Posts: 78
So you're after the table like this (from the "wrong" CPU tho)?:

http://oms.wmhost.com/misc/6502_inst.png
2012-03-02 18:28
chatGPZ

Registered: Dec 2001
Posts: 11386
Quote:
Exactly + less code to implement it probably given you implement the ~130 sub operation (compared to 256 special case instruction as we do today more or less)

not really... if you look at a typical cycle exact cpu core, it already works with a lookuptable and sub operations very similar to what the cpu does :)
2012-03-02 22:55
JackAsser

Registered: Jun 2002
Posts: 2014
Quote: So you're after the table like this (from the "wrong" CPU tho)?:

http://oms.wmhost.com/misc/6502_inst.png


Yes, but I have deciphered the die-scan now into a proper table. There are errors though that I must fix first.
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